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document no. u17260ej3v1ud00 (3rd edition) date published august 2005 n cp(k) printed in japan 2004 pd78f0531 pd78f0532 pd78f0533 pd78f0534 pd78f0535 pd78f0536 pd78f0537 pd78f0537d 78k0/ke2 8-bit single-chip microcontrollers preliminary user?s manual the pd78f0537d has an on-chip debug function. do not use this product for mass production because its reliab ility cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of ti mes the flash memory can be rewritten. nec electronics does not accept complaints concerning this product.
preliminary user?s manual u17260ej3v1ud 2 [memo]
preliminary user?s manual u17260ej3v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
preliminary user?s manual u17260ej3v1ud 4 eeprom is a trademark of nec electronics corporation. windows and windows nt are registered trademarks or trademarks of microsoft co rporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. superflash ? is a registered tradem ark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics products depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. ? ? ? ? ? ? ? m5d 02. 11-1 the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
preliminary user?s manual u17260ej3v1ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
preliminary user?s manual u17260ej3v1ud 6 introduction readers this manual is intended for user engineer s who wish to understand the functions of the 78k0/ke2 and design and develop application systems and programs for these devices. the target products are as follows. 78k0/ke2: pd78f0531, 78f0532, 78f0533, 78f053 4, 78f0535, 78f0536, 78f0537, 78f0537d purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the 78k0/ke2 manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). 78k0/ke2 user?s manual (this manual) 78k/0 series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications (target) ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this ma nual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to gain a general understanding of functions: read this manual in the order of the contents . the mark shows major revised points. ? how to interpret the register format: for a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the ra78k0, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0. ? to check the details of a register when you know the register name: see appendix c register index . ? to know details of the 78k/0 series instructions: refer to the separate document 78k/0 series instructions user?s manual (u12326e) .
preliminary user?s manual u17260ej3v1ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pu blication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0/ke2 user?s manual this manual 78k/0 series instructions user?s manual u12326e documents related to development tools (software) (user?s manuals) document name document no. operation u17199e language u17198e ra78k0 ver. 3.80 assembler package structured assembly language u17197e operation u17201e cc78k0 ver. 3.70 c compiler language u17200e operation u17246e sm+ system simulator external part user open interface specifications u17247e id78k0-qb ver. 2.90 integrat ed debugger operation u17437e pm+ ver. 5.20 u16934e documents related to development tools (hardware) (user?s manuals) document name document no. qb-78k0kx2 in-circuit emulator u17341e qb-78k0mini on-chip debug emulator u17029e documents related to fl ash memory programming document name document no. pg-fp4 flash memory programmer user?s manual u15260e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing.
preliminary user?s manual u17260ej3v1ud 8 other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device m ount manual? website (h ttp://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing.
preliminary user?s manual u17260ej3v1ud 9 contents chapter 1 outline ........................................................................................................... ................. 17 1.1 features ................................................................................................................... ................. 17 1.2 applications ............................................................................................................... .............. 18 1.3 ordering information ....................................................................................................... ........ 19 1.4 pin configuration (top view).................................. ............................................................. ... 23 1.5 78k0/kx2 series lineup ..................................................................................................... ..... 26 1.6 block diagram.............................................................................................................. ............ 29 1.7 outline of functions ....................................................................................................... ......... 30 chapter 2 pin functions .................................................................................................... ........... 32 2.1 pin function list.......................................................................................................... ............ 32 2.2 description of pin functions .................................... ........................................................... ... 36 2.2.1 p00 to p06 (por t 0)...................................................................................................... ...............36 2.2.2 p10 to p17 (por t 1)...................................................................................................... ...............37 2.2.3 p20 to p27 (por t 2)...................................................................................................... ...............38 2.2.4 p30 to p33 (por t 3)...................................................................................................... ...............38 2.2.5 p40 to p43 (por t 4)...................................................................................................... ...............39 2.2.6 p50 to p53 (por t 5)...................................................................................................... ...............39 2.2.7 p60 to p63 (por t 6)...................................................................................................... ...............39 2.2.8 p70 to p77 (por t 7)...................................................................................................... ...............39 2.2.9 p120 to p124 (por t 12)................................................................................................... ............40 2.2.10 p130 (port 13) .......................................................................................................... ..................40 2.2.11 p140, p1 41 (port 14).................................................................................................... ..............41 2.2.12 av ref ............................................................................................................................... ..........41 2.2.13 av ss ............................................................................................................................... ............41 2.2.14 reset ................................................................................................................... ....................41 2.2.15 regc.................................................................................................................... .....................41 2.2.16 v dd and ev dd .............................................................................................................................42 2.2.17 v ss and ev ss .............................................................................................................................42 2.2.18 flmd0 ................................................................................................................... ....................42 2.3 pin i/o circuits and recommended connection of unused pins....................................... 43 chapter 3 cpu architecture ................................................................................................. ..... 47 3.1 memory space............................................................................................................... ........... 47 3.1.1 internal progr am memory space ............................................................................................ ....56 3.1.2 memory bank ( pd78f0536, 78f05 37, and 78f0537d only)....................................................58 3.1.3 internal data memory space............................................................................................... ........58 3.1.4 special function register (s fr) area ..................................................................................... .....59 3.1.5 data memo ry addre ssing ................................................................................................... ........59 3.2 processor registers ........................................................................................................ ........ 67 3.2.1 control registers........................................................................................................ .................67 3.2.2 general-purpo se regi sters ................................................................................................ .........71 3.2.3 special function register s (sfrs)........................................................................................ .......72
preliminary user?s manual u17260ej3v1ud 10 3.3 instruction address addressing ..................................... ....................................................... 7 7 3.3.1 relative addre ssing ...................................................................................................... ............. 77 3.3.2 immediat e addre ssing ..................................................................................................... .......... 78 3.3.3 table indi rect addr essing ................................................................................................ .......... 79 3.3.4 register addre ssing ...................................................................................................... ............ 79 3.4 operand address addre ssing ................................................................................................ 8 0 3.4.1 impli ed addres sing ....................................................................................................... ............. 80 3.4.2 register addre ssing ...................................................................................................... ............ 81 3.4.3 direct addre ssing ........................................................................................................ .............. 82 3.4.4 short dire ct addressing .................................................................................................. ........... 83 3.4.5 special function r egister (sfr ) addre ssing ............................................................................... 84 3.4.6 register i ndirect addr essing............................................................................................. ......... 85 3.4.7 based addres sing......................................................................................................... ............. 86 3.4.8 based index ed addres sing ................................................................................................. ....... 87 3.4.9 stack addressi ng......................................................................................................... .............. 88 chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) ......................................................... 89 4.1 memory bank................................................................................................................ ............ 89 4.2 memory bank select register (bank)................................................................................... 90 4.3 selecting memory bank...................................................................................................... ..... 91 4.3.1 referencing values between memory banks............................................................................. 91 4.3.2 branching instruction between memo ry bank s.......................................................................... 93 4.3.3 subroutine call bet ween memory banks.................................................................................... 9 5 4.3.4 instruction branch to bank area by inte rrupt ............................................................................. .97 chapter 5 port functions ................................................................................................... ........ 99 5.1 port functions ............................................................................................................. ............. 99 5.2 port configurat ion ......................................................................................................... ........ 101 5.2.1 port 0................................................................................................................... .....................102 5.2.2 port 1................................................................................................................... .....................108 5.2.3 port 2................................................................................................................... .....................113 5.2.4 port 3................................................................................................................... .....................114 5.2.5 port 4................................................................................................................... .....................116 5.2.6 port 5................................................................................................................... .....................117 5.2.7 port 6................................................................................................................... .....................118 5.2.8 port 7................................................................................................................... .....................120 5.2.9 po rt 12.................................................................................................................. ....................121 5.2.10 po rt 13................................................................................................................. .....................123 5.2.11 po rt 14................................................................................................................. .....................124 5.3 registers controlling port functi on .................................................................................... 125 5.4 port function operations................................................. .................................................. ... 130 5.4.1 writing to i/o port ...................................................................................................... ...............130 5.4.2 reading from i/o port.................................................................................................... ...........130 5.4.3 operatio ns on i/o port................................................................................................... ...........130 5.5 settings of port mode register and output latch when using alternate function....... 131 chapter 6 clock generator .................................................................................................. .. 134
preliminary user?s manual u17260ej3v1ud 11 6.1 functions of clock generator .... .......................................................................................... 1 34 6.2 configuration of clock generato r........................................................................................ 135 6.3 registers controlling clock generator ................. .............................................................. 137 6.4 system clock oscillator.................................................................................................... .... 146 6.4.1 x1 o scillat or ............................................................................................................ .................146 6.4.2 xt1 o scillato r ........................................................................................................... ................146 6.4.3 when subsystem clock is not us ed ......................................................................................... .149 6.4.4 internal high- speed osci llator ........................................................................................... ........149 6.4.5 internal lo w-speed osc illat or............................................................................................ .........149 6.4.6 pre scaler................................................................................................................ ..................149 6.5 clock generator operation ..................................... ............................................................. . 150 6.6 controlling clock .......................................................................................................... ......... 153 6.6.1 controlling high -speed system clock...................................................................................... ..153 6.6.2 example of controlling internal high-speed oscill ation cl ock .....................................................156 6.6.3 example of contro lling subsyste m clock................................................................................... 158 6.6.4 example of controlling intern al low-speed osc illation cl ock ......................................................160 6.6.5 clocks supplied to cp u and peripheral hardwar e....................................................................160 6.6.6 cpu clock status transitio n diagr am ...................................................................................... ..161 6.6.7 condition bef ore changing cpu clock and processing after c hanging cpu clock ...................166 6.6.8 time required for switchover of cpu clock and main system cl ock .........................................167 6.6.9 conditions before clock oscillation is stopped..........................................................................1 68 6.6.10 peripheral hardw are and source clocks ................................................................................... 169 chapter 7 16-bit timer/event counters 00 and 01 ........................................................ 170 7.1 functions of 16-bit time r/event counters 00 and 01 ............... ......................................... 170 7.2 configuration of 16-bit timer/ event counters 00 and 01................. ................................. 171 7.3 registers controlling 16-bit ti mer/event counters 00 and 01 ........ ................................. 176 7.4 operation of 16-bit timer/event counters 00 and 01 ........................................................ 188 7.4.1 interval ti mer operation ................................................................................................. ...........188 7.4.2 square wave output oper ation ............................................................................................. ....191 7.4.3 external event counter o peration ......................................................................................... ....194 7.4.4 operation in clear & start mode entered by ti00n pin va lid edge in put....................................197 7.4.5 free-running timer oper ation............................................................................................. .......213 7.4.6 ppg output operation..................................................................................................... ..........222 7.4.7 one-shot puls e output op eration.......................................................................................... ....225 7.4.8 pulse width me asurement operati on ........................................................................................ 230 7.5 special use of tm0n ........................................................................................................ ...... 239 7.5.1 rewriting cr01n dur ing tm0n oper ation .................................................................................239 7.5.2 setting l vs0n and lv r0n .................................................................................................. .....239 7.6 cautions for 16-bit timer/event counters 00 and 01......................................................... 241 chapter 8 8-bit timer/event counters 50 and 51 .......................................................... 245 8.1 functions of 8-bit time r/event counters 50 and 51 ................. ......................................... 245 8.2 configuration of 8-bit timer/ event counters 50 and 51................. ................................... 245 8.3 registers controlling 8- bit timer/event c ounters 50 and 51 ................... ........................ 248 8.4 operations of 8-bit timer/event counters 50 an d 51 ........................................................ 253 8.4.1 operation as interval timer .............................................................................................. .........253 8.4.2 operation as ex ternal event count er ...................................................................................... ..255
preliminary user?s manual u17260ej3v1ud 12 8.4.3 square-wave output oper ation ............................................................................................. ....256 8.4.4 pwm output operat ion..................................................................................................... .........257 8.5 cautions for 8-bit timer/event counters 50 and 51 ........................................................... 261 chapter 9 8-bit timers h0 and h1 ........................................................................................ .. 262 9.1 functions of 8-bit timers h0 and h1 ......................... .......................................................... 262 9.2 configuration of 8-bit timers h0 and h1............... .............................................................. 262 9.3 registers controlling 8-bit timers h0 and h1 ...... .............................................................. 266 9.4 operation of 8-bit timers h0 and h1 ......................... .......................................................... 271 9.4.1 operation as interval timer/square-wa ve out put ....................................................................... 271 9.4.2 operation as pwm output .................................................................................................. ......274 9.4.3 carrier generator operati on (8-bit timer h1 only )......................................................................28 0 chapter 10 watch timer..................................................................................................... ......... 287 10.1 functions of watch timer .................................................................................................. ... 287 10.2 configuration of watch time r.............................................................................................. . 288 10.3 register controlling watch timer ........................................................................................ 28 9 10.4 watch timer operations.................................................................................................... .... 291 10.4.1 watch time r operation ................................................................................................... ...........291 10.4.2 interval ti mer operation................................................................................................ .............291 10.5 cautions for watch timer .................................................................................................. ... 292 chapter 11 watchdog timer .................................................................................................. ... 293 11.1 functions of watchdog timer .............................................................................................. 2 93 11.2 configuration of watchdog timer ................................ ........................................................ 294 11.3 register controlling watchdog timer ......................... ........................................................ 295 11.4 operation of watchdog timer............................................................................................... 296 11.4.1 controlling operat ion of watc hdog ti mer ................................................................................. ..296 11.4.2 setting overflow ti me of watc hdog ti mer................................................................................. ..297 11.4.3 setting window open period of watchdo g time r ........................................................................298 chapter 12 clock output/buzzer output controller............................................... 300 12.1 functions of clock outp ut/buzzer output controlle r ........................................................ 300 12.2 configuration of clock output /buzzer output controller ................................................. 301 12.3 registers controlling clock output/buzzer outp ut controller......................................... 301 12.4 operations of clock output/buzzer output cont roller ...................................................... 303 12.4.1 operation as clo ck out put............................................................................................... ..........303 12.4.2 operation as buzzer output .............................................................................................. ........303 chapter 13 a/d converter ................................................................................................... ...... 304 13.1 function of a/d converter ................................................................................................. ... 304 13.2 configuration of a/d converter .............................. .............................................................. 305 13.3 registers used in a/d converter.......................................................................................... 3 07 13.4 a/d converter operations .................................................................................................. ... 315 13.4.1 basic operations of a/d c onverter ....................................................................................... .....315 13.4.2 input volt age and conversi on results .................................................................................... ....317
preliminary user?s manual u17260ej3v1ud 13 13.4.3 a/d converte r operati on mode ............................................................................................ .....318 13.5 how to read a/d converter char acteristics table ............................................................ 320 13.6 cautions for a/d converter................................................................................................ ... 322 chapter 14 serial interface uart0 ...................................................................................... 326 14.1 functions of serial interface uart0 .......................... ......................................................... 326 14.2 configuration of serial interfac e uart0 ............................................................................. 327 14.3 registers controlling serial interface uart0 ...... .............................................................. 330 14.4 operation of serial interface uart0........................ ............................................................ 335 14.4.1 operatio n stop mode..................................................................................................... ...........335 14.4.2 asynchronous serial interface (uar t) m ode ........................................................................... 336 14.4.3 dedicated baud rate generator ........................................................................................... .....342 chapter 15 serial interface uart6 ...................................................................................... 347 15.1 functions of serial interface uart6 .......................... ......................................................... 347 15.2 configuration of serial interfac e uart6 ............................................................................. 351 15.3 registers controlling serial interface uart6 ...... .............................................................. 354 15.4 operation of serial interface uart6........................ ............................................................ 363 15.4.1 operatio n stop mode..................................................................................................... ...........363 15.4.2 asynchronous serial interface (uar t) m ode ........................................................................... 364 15.4.3 dedicated baud rate generator ........................................................................................... .....377 chapter 16 serial interfaces csi10 and csi11................................................................ 384 16.1 functions of serial interfaces csi 10 and csi11 ................................................................. 384 16.2 configuration of serial interfaces csi10 and csi1 1 .......................................................... 385 16.3 registers controlling serial interfaces csi10 a nd csi11.................................................. 388 16.4 operation of serial interfaces cs i10 and csi11 ................................................................. 393 16.4.1 operatio n stop mode..................................................................................................... ...........393 16.4.2 3-wire se rial i/o mode .................................................................................................. ............394 chapter 17 serial interface iic0 .......................................................................................... . 406 17.1 functions of serial interface iic0............................. ........................................................... . 406 17.2 configuration of serial interfac e iic0 .................................................................................. 40 9 17.3 registers to control serial interface iic0............. ............................................................... 412 17.4 i 2 c bus mode functions ........................................................................................................ 425 17.4.1 pin conf iguration ....................................................................................................... ...............425 17.5 i 2 c bus definitions and control methods................... ......................................................... 426 17.5.1 start conditi ons ........................................................................................................ ................426 17.5.2 addr esses ............................................................................................................... .................427 17.5.3 transfer direct ion specif ication ........................................................................................ ........427 17.5.4 acknowle dge (ack) ....................................................................................................... ..........428 17.5.5 stop c onditio n .......................................................................................................... ................429 17.5.6 wait.................................................................................................................... ......................430 17.5.7 cance ling wa it.......................................................................................................... ................432 17.5.8 interrupt request (intiic0) generation timing and wa it cont rol.................................................432 17.5.9 address matc h detection method.......................................................................................... ...433 17.5.10 erro r detec tion ........................................................................................................ .................433
preliminary user?s manual u17260ej3v1ud 14 17.5.11 ext ension code......................................................................................................... ................434 17.5.12 arbi tration............................................................................................................ .....................435 17.5.13 wak eup func tion........................................................................................................ ...............436 17.5.14 communicati on reservation.............................................................................................. ........437 17.5.15 other caut ions ......................................................................................................... .................440 17.5.16 communica tion oper ations............................................................................................... ........442 17.5.17 timing of i 2 c interrupt request (i ntiic0) occu rrence ................................................................449 17.6 timing charts ............................................................................................................. ............ 470 chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) .................... 477 18.1 functions of multiplier/divider ............................... ............................................................ .. 477 18.2 configuration of multiplier/d ivider ....................................................................................... 477 18.3 register controlling multiplie r/divider ................................................................................ 481 18.4 operations of multiplier/divi der.......................................................................................... .. 482 18.4.1 multiplicati on operation................................................................................................ .............482 18.4.2 division operat ion...................................................................................................... ...............484 chapter 19 interrupt functions ............................................................................................ 4 86 19.1 interrupt function types.................................................................................................. ..... 486 19.2 interrupt sources and configuration ........................... ........................................................ 486 19.3 registers controlling interrupt functions .......................................................................... 491 19.4 interrupt servicing operations ............................................................................................ . 499 19.4.1 maskable interrupt acknowl edgement ...................................................................................... 499 19.4.2 software interrupt r equest acknow ledgement ..........................................................................501 19.4.3 multiple inte rrupt servicing............................................................................................ ............502 19.4.4 interrupt request hold .................................................................................................. .............505 chapter 20 key interrupt function ..................................................................................... 506 20.1 functions of key interrupt ............................................ .................................................... .... 506 20.2 configuration of key interrupt............................................................................................ .. 506 20.3 register controlling key interrupt ............................. .......................................................... 5 07 chapter 21 standby function ................................................................................................ .. 508 21.1 standby function and configurat ion................................................................................... 508 21.1.1 standby function........................................................................................................ ...............508 21.1.2 registers contro lling standby function.................................................................................. ....508 21.2 standby function operation................................................................................................ . 511 21.2.1 halt mode ............................................................................................................... ...............511 21.2.2 stop mode ............................................................................................................... ..............516 chapter 22 reset function.................................................................................................. ...... 521 22.1 register for confirming reset source................................................................................. 529 chapter 23 power-on-clear circuit...................................................................................... 530 23.1 functions of power-on-c lear circuit ................................................................................... 530
preliminary user?s manual u17260ej3v1ud 15 23.2 configuration of power-on-clear circuit............................................................................. 531 23.3 operation of power-on-clear circuit ..................... .............................................................. 531 23.4 cautions for power-on-clear ci rcuit.................................................................................... 534 chapter 24 low-voltage detector ....................................................................................... 536 24.1 functions of low-voltage detector ..................................................................................... 536 24.2 configuration of low-voltage de tector............................................................................... 536 24.3 registers controlling low-voltage detector ...................................................................... 537 24.4 operation of low-voltage detector ......................... ............................................................ 540 24.4.1 when used as re set ...................................................................................................... ...........541 24.4.2 when used as inte rrupt .................................................................................................. ..........546 24.5 cautions for low-voltage detector.......................... ............................................................ 551 chapter 25 option byte..................................................................................................... .......... 554 25.1 functions of option bytes ......................... ........................................................................... 55 4 25.2 format of option byte .......................................................................................................... . 555 chapter 26 flash memory.................................................................................................... ...... 558 26.1 internal memory size switching register ............. .............................................................. 558 26.2 internal expansion ram size switching register.. ............................................................ 560 26.3 writing with flash programmer ........................................................................................... 56 1 26.4 programming environment................................................................................................... 564 26.5 communication mode ........................................................................................................ ... 564 26.6 handling of pins on board................................................................................................. ... 566 26.6.1 flmd 0 pi n ............................................................................................................... ................566 26.6.2 serial in terface pins................................................................................................... ...............566 26.6.3 reset pin ............................................................................................................... ................568 26.6.4 port pi ns............................................................................................................... ....................568 26.6.5 regc pin................................................................................................................ .................568 26.6.6 other signal pins ....................................................................................................... ...............568 26.6.7 powe r supply ............................................................................................................ ...............568 26.7 programming method........................................................................................................ .... 569 26.7.1 controllin g flash memory ................................................................................................ .........569 26.7.2 flash memory programming mode ..........................................................................................5 69 26.7.3 selecting co mmunicati on mode ............................................................................................ ...570 26.7.4 communicati on commands.................................................................................................. ....571 26.8 security settings......................................................................................................... ........... 572 26.9 flash memory programming by self-programming.. ......................................................... 574 26.9.1 boot sw ap func tion...................................................................................................... .............576 chapter 27 on-chip debug function ( pd78f0537d only) ............................................ 578 27.1 on-chip debug security id................................................................................................. .. 579 chapter 28 instruction set ................................................................................................. ..... 580 28.1 conventions used in operation list...................... .............................................................. 580 28.1.1 operand identifiers and specification method s ........................................................................580
preliminary user?s manual u17260ej3v1ud 16 28.1.2 description of operation column ......................................................................................... ......581 28.1.3 description of fl ag operati on colu mn .................................................................................... ....581 28.2 operation list ............................................................................................................ ............. 582 28.3 instructions listed by addressing type ................... .......................................................... 590 chapter 29 electrical specifications (target).............................................................. 593 chapter 30 package drawings ................................................................................................ 612 chapter 31 cautions for wait.............................................................................................. ... 617 31.1 cautions for wait......................................................................................................... ........... 617 31.2 peripheral hardware that generates wait ................ .......................................................... 618 appendix a development tools............................................................................................... 619 a.1 software package ........................................................................................................... ....... 622 a.2 language processing so ftware............................................................................................ 622 a.3 control software ........................................................................................................... ......... 623 a.4 flash memory writing tools ................................................................................................. 623 a.5 debugging tools (hardware) ................................................................................................ 6 24 a.5.1 when using in-circuit emulator qb -78k0 kx2........................................................................... 624 a.5.2 when using on-c hip debug emulator qb-78k0m ini.................................................................625 a.6 debugging tools (software) ................................................................................................. 625 appendix b notes on target system design ................................................................... 626 appendix c register index .................................................................................................. ....... 628 c.1 register index (in alphabetical order with respect to register names) ........................ 628 c.2 register index (in alphabetical order with re spect to register symbol) ....................... 632 appendix d revision history ................................................................................................ ..... 636 d.1 major revisions in this edition............................................................................................ 636 d.2 revisions history up to previous edition ................. .......................................................... 643
preliminary user?s manual u17260ej3v1ud 17 chapter 1 outline 1.1 features { minimum instruction execution time can be changed from high speed (0.1 s: @ 20 mhz operation with high- speed system clock) to ultra low-speed (122 s: @ 32.768 khz operation with subsystem clock) { general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) { rom, ram capacities data memory item part number program memory (rom) internal high-speed ram note internal expansion ram note pd78f0531 16 kb 768 bytes pd78f0532 24 kb pd78f0533 32 kb ? pd78f0534 48 kb 1 kb pd78f0535 60 kb 2 kb pd78f0536 96 kb 4 kb pd78f0537, 78f0537d flash memory note 128 kb 1 kb 6 kb note the internal flash memory, internal high-speed ram capacities, and internal expansion ram capacities can be changed using the internal memory size swit ching register (ims) and the internal expansion ram size switching register (i xs). for ims and ixs, see 26.1 memory size switching register and 26.2 internal expansion ram size switching register . { on-chip single-power-supply flash memory { self-programming (with boot swap function) { on-chip debug function ( pd78f0537d only) note { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { on-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock) { on-chip multiplier/divider (16 bits 16 bits, 32 bits / 16 bits) ( pd78f0534, 78f0535, 78f0536, 78f0537, 78f0537d only) { on-chip key interrupt function { on-chip clock output/buzzer output controller { i/o ports: 55 (n-ch open drain: 4) note the pd78f0537d has an on-chip debug function. do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, from the viewpoint of the restriction on the number of times the flash memory can be rewritten. nec electronics does not accept any complaint about this product.
chapter 1 outline preliminary user?s manual u17260ej3v1ud 18 { timer pd78f0531, 78f0532, 78f 0533: 7 channels pd78f0534, 78f0535, 78f0536, 78f0537, 78f0537d: 8 channels ? 16-bit timer/event counter: 2 channels note ? 8-bit timer/event counter: 2 channels ? 8-bit timer: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel note pd78f0531, 78f0532, 78f0533: 1 channel { serial interface pd78f0531, 78f0532, 78f 0533: 3 channels pd78f0534, 78f0535, 78f0536, 78f0537, 78f0537d: 4 channels ? uart (lin (local interconnect network)-bus supported: 1 channel ? csi/uart note1 : 1 channel ? csi note2 : 1 channel ? i 2 c: 1 channel notes 1. select either of the functions of these alternate-function pins. 2. pd78f0534, 78f0535, 78f0536 , 78f0537, 78f0537d only { 10-bit resolution a/d converter (av ref = 2.3 to 5.5 v): 8 channels { power supply voltage: v dd = 1.8 to 5.5 v { operating ambient temperature: ? t a = ? 40 to +85 c: (t), (s), (r) products ? t a = ? 40 to +125 c: (t2) product 1.2 applications { automotive equipment ((a), (a1), (a2) grade products, under development) ? system control for body electricals (power windows, keyless entry reception, etc.) ? sub-microcontrollers for control { car audio { av equipment, home audio { pc peripheral equipment (keyboards, etc.) { household electrical appliances ? air conditioners ? microwave ovens, electric rice cookers { industrial equipment ? pumps ? vending machines ? fa (factory automation)
chapter 1 outline preliminary user?s manual u1260ej3v1ud 19 1.3 ordering information ? flash memory version (1/4) part number package pd78f0531gb(t)-ueu-a 64-pin plastic lqfp (10x10) pd78f0531gb(t2)-ueu-a 64-pin plastic lqfp (10x10) pd78f0531gb(s)-ueu-a 64-pin plastic lqfp (10x10) pd78f0531gb(r)-ueu-a 64-pin plastic lqfp (10x10) pd78f0531gc(t)-ubs-a 64-pin plastic lqfp (14x14) pd78f0531gc(t2)-ubs-a 64-pin plastic lqfp (14x14) pd78f0531gc(s)-ubs-a 64-pin plastic lqfp (14x14) pd78f0531gc(r)-ubs-a 64-pin plastic lqfp (14x14) pd78f0531gk(t)-uet-a 64-pin plastic lqfp (12x12) pd78f0531gk(t2)-uet-a 64-pin plastic lqfp (12x12) pd78f0531gk(s)-uet-a 64-pin plastic lqfp (12x12) pd78f0531gk(r)-uet-a 64-pin plastic lqfp (12x12) pd78f0531ga(t)-9ev-a 64-pin plastic tqfp (7x7) pd78f0531ga(t2)-9ev-a 64-pin plastic tqfp (7x7) pd78f0531ga(s)-9ev-a 64-pin plastic tqfp (7x7) pd78f0531ga(r)-9ev-a 64-pin plastic tqfp (7x7) pd78f0531fc(t)-aa1-a 64-pin plastic flga (5x5) pd78f0531fc(s)-aa1-a 64-pin plastic flga (5x5) pd78f0531fc(r)-aa1-a 64-pin plastic flga (5x5) pd78f0532gb(t)-ueu-a 64-pin plastic lqfp (10x10) pd78f0532gb(t2)-ueu-a 64-pin plastic lqfp (10x10) pd78f0532gb(s)-ueu-a 64-pin plastic lqfp (10x10) pd78f0532gb(r)-ueu-a 64-pin plastic lqfp (10x10) pd78f0532gc(t)-ubs-a 64-pin plastic lqfp (14x14) pd78f0532gc(t2)-ubs-a 64-pin plastic lqfp (14x14) pd78f0532gc(s)-ubs-a 64-pin plastic lqfp (14x14) pd78f0532gc(r)-ubs-a 64-pin plastic lqfp (14x14) pd78f0532gk(t)-uet-a 64-pin plastic lqfp (12x12) pd78f0532gk(t2)-uet-a 64-pin plastic lqfp (12x12) pd78f0532gk(s)-uet-a 64-pin plastic lqfp (12x12) pd78f0532gk(r)-uet-a 64-pin plastic lqfp (12x12) pd78f0532ga(t)-9ev-a 64-pin plastic tqfp (7x7) pd78f0532ga(t2)-9ev-a 64-pin plastic tqfp (7x7) pd78f0532ga(s)-9ev-a 64-pin plastic tqfp (7x7) pd78f0532ga(r)-9ev-a 64-pin plastic tqfp (7x7) pd78f0532fc(t)-aa1-a 64-pin plastic flga (5x5) pd78f0532fc(s)-aa1-a 64-pin plastic flga (5x5) pd78f0532fc(r)-aa1-a 64-pin plastic flga (5x5)
chapter 1 outline preliminary user?s manual u17260ej3v1ud 20 ? flash memory version (2/4) part number package pd78f0533gb(t)-ueu-a 64-pin plastic lqfp (10x10) pd78f0533gb(t2)-ueu-a 64-pin plastic lqfp (10x10) pd78f0533gb(s)-ueu-a 64-pin plastic lqfp (10x10) pd78f0533gb(r)-ueu-a 64-pin plastic lqfp (10x10) pd78f0533gc(t)-ubs-a 64-pin plastic lqfp (14x14) pd78f0533gc(t2)-ubs-a 64-pin plastic lqfp (14x14) pd78f0533gc(s)-ubs-a 64-pin plastic lqfp (14x14) pd78f0533gc(r)-ubs-a 64-pin plastic lqfp (14x14) pd78f0533gk(t)-uet-a 64-pin plastic lqfp (12x12) pd78f0533gk(t2)-uet-a 64-pin plastic lqfp (12x12) pd78f0533gk(s)-uet-a 64-pin plastic lqfp (12x12) pd78f0533gk(r)-uet-a 64-pin plastic lqfp (12x12) pd78f0533ga(t)-9ev-a 64-pin plastic tqfp (7x7) pd78f0533ga(t2)-9ev-a 64-pin plastic tqfp (7x7) pd78f0533ga(s)-9ev-a 64-pin plastic tqfp (7x7) pd78f0533ga(r)-9ev-a 64-pin plastic tqfp (7x7) pd78f0533fc(t)-aa1-a 64-pin plastic flga (5x5) pd78f0533fc(s)-aa1-a 64-pin plastic flga (5x5) pd78f0533fc(r)-aa1-a 64-pin plastic flga (5x5) pd78f0534gb(t)-ueu-a 64-pin plastic lqfp (10x10) pd78f0534gb(t2)-ueu-a 64-pin plastic lqfp (10x10) pd78f0534gb(s)-ueu-a 64-pin plastic lqfp (10x10) pd78f0534gb(r)-ueu-a 64-pin plastic lqfp (10x10) pd78f0534gc(t)-ubs-a 64-pin plastic lqfp (14x14) pd78f0534gc(t2)-ubs-a 64-pin plastic lqfp (14x14) pd78f0534gc(s)-ubs-a 64-pin plastic lqfp (14x14) pd78f0534gc(r)-ubs-a 64-pin plastic lqfp (14x14) pd78f0534gk(t)-uet-a 64-pin plastic lqfp (12x12) pd78f0534gk(t2)-uet-a 64-pin plastic lqfp (12x12) pd78f0534gk(s)-uet-a 64-pin plastic lqfp (12x12) pd78f0534gk(r)-uet-a 64-pin plastic lqfp (12x12) pd78f0534ga(t)-9ev-a 64-pin plastic tqfp (7x7) pd78f0534ga(t2)-9ev-a 64-pin plastic tqfp (7x7) pd78f0534ga(s)-9ev-a 64-pin plastic tqfp (7x7) pd78f0534ga(r)-9ev-a 64-pin plastic tqfp (7x7) pd78f0534fc(t)-aa1-a 64-pin plastic flga (5x5) pd78f0534fc(s)-aa1-a 64-pin plastic flga (5x5) pd78f0534fc(r)-aa1-a 64-pin plastic flga (5x5)
chapter 1 outline preliminary user?s manual u1260ej3v1ud 21 ? flash memory version (3/4) part number package pd78f0535gb(t)-ueu-a 64-pin plastic lqfp (10x10) pd78f0535gb(t2)-ueu-a 64-pin plastic lqfp (10x10) pd78f0535gb(s)-ueu-a 64-pin plastic lqfp (10x10) pd78f0535gb(r)-ueu-a 64-pin plastic lqfp (10x10) pd78f0535gc(t)-ubs-a 64-pin plastic lqfp (14x14) pd78f0535gc(t2)-ubs-a 64-pin plastic lqfp (14x14) pd78f0535gc(s)-ubs-a 64-pin plastic lqfp (14x14) pd78f0535gc(r)-ubs-a 64-pin plastic lqfp (14x14) pd78f0535gk(t)-uet-a 64-pin plastic lqfp (12x12) pd78f0535gk(t2)-uet-a 64-pin plastic lqfp (12x12) pd78f0535gk(s)-uet-a 64-pin plastic lqfp (12x12) pd78f0535gk(r)-uet-a 64-pin plastic lqfp (12x12) pd78f0535ga(t)-9ev-a 64-pin plastic tqfp (7x7) pd78f0535ga(t2)-9ev-a 64-pin plastic tqfp (7x7) pd78f0535ga(s)-9ev-a 64-pin plastic tqfp (7x7) pd78f0535ga(r)-9ev-a 64-pin plastic tqfp (7x7) pd78f0535fc(t)-aa1-a 64-pin plastic flga (5x5) pd78f0535fc(s)-aa1-a 64-pin plastic flga (5x5) pd78f0535fc(r)-aa1-a 64-pin plastic flga (5x5) pd78f0536gb(t)-ueu-a 64-pin plastic lqfp (10x10) pd78f0536gb(t2)-ueu-a 64-pin plastic lqfp (10x10) pd78f0536gb(s)-ueu-a 64-pin plastic lqfp (10x10) pd78f0536gb(r)-ueu-a 64-pin plastic lqfp (10x10) pd78f0536gc(t)-ubs-a 64-pin plastic lqfp (14x14) pd78f0536gc(t2)-ubs-a 64-pin plastic lqfp (14x14) pd78f0536gc(s)-ubs-a 64-pin plastic lqfp (14x14) pd78f0536gc(r)-ubs-a 64-pin plastic lqfp (14x14) pd78f0536gk(t)-uet-a 64-pin plastic lqfp (12x12) pd78f0536gk(t2)-uet-a 64-pin plastic lqfp (12x12) pd78f0536gk(s)-uet-a 64-pin plastic lqfp (12x12) pd78f0536gk(r)-uet-a 64-pin plastic lqfp (12x12) pd78f0536ga(t)-9ev-a 64-pin plastic tqfp (7x7) pd78f0536ga(t2)-9ev-a 64-pin plastic tqfp (7x7) pd78f0536ga(s)-9ev-a 64-pin plastic tqfp (7x7) pd78f0536ga(r)-9ev-a 64-pin plastic tqfp (7x7) pd78f0536fc(t)-aa1-a 64-pin plastic flga (5x5) pd78f0536fc(s)-aa1-a 64-pin plastic flga (5x5) pd78f0536fc(r)-aa1-a 64-pin plastic flga (5x5)
chapter 1 outline preliminary user?s manual u17260ej3v1ud 22 ? flash memory version (4/4) part number package pd78f0537gb(t)-ueu-a 64-pin plastic lqfp (10x10) pd78f0537gb(t2)-ueu-a 64-pin plastic lqfp (10x10) pd78f0537gb(s)-ueu-a 64-pin plastic lqfp (10x10) pd78f0537gb(r)-ueu-a 64-pin plastic lqfp (10x10) pd78f0537gc(t)-ubs-a 64-pin plastic lqfp (14x14) pd78f0537gc(t2)-ubs-a 64-pin plastic lqfp (14x14) pd78f0537gc(s)-ubs-a 64-pin plastic lqfp (14x14) pd78f0537gc(r)-ubs-a 64-pin plastic lqfp (14x14) pd78f0537gk(t)-uet-a 64-pin plastic lqfp (12x12) pd78f0537gk(t2)-uet-a 64-pin plastic lqfp (12x12) pd78f0537gk(s)-uet-a 64-pin plastic lqfp (12x12) pd78f0537gk(r)-uet-a 64-pin plastic lqfp (12x12) pd78f0537ga(t)-9ev-a 64-pin plastic tqfp (7x7) pd78f0537ga(t2)-9ev-a 64-pin plastic tqfp (7x7) pd78f0537ga(s)-9ev-a 64-pin plastic tqfp (7x7) pd78f0537ga(r)-9ev-a 64-pin plastic tqfp (7x7) pd78f0537fc(t)-aa1-a 64-pin plastic flga (5x5) pd78f0537fc(s)-aa1-a 64-pin plastic flga (5x5) pd78f0537fc(r)-aa1-a 64-pin plastic flga (5x5) pd78f0537dgb(t)-ueu-a note 64-pin plastic lqfp (10x10) pd78f0537dgc(t)-ubs-a note 64-pin plastic lqfp (14x14) pd78f0537dgk(t)-uet-a note 64-pin plastic lqfp (12x12) pd78f0537dga(t)-9ev-a note 64-pin plastic tqfp (7x7) pd78f0537dfc(t)-aa1-a note 64-pin plastic flga (5x5) note the pd78f0537d has an on-chip debug function. do no t use this product for mass production, because its reliability cannot be guaranteed after the on-chip debug function has been used, with respect to the number of times the flash memory can be rewritten. nec electronics does not accept complaints about this product. remark products with -a at the end of the part number are lead-free products. the standard quality versions of this product ar e classified by production process as follows. (t), (t2): general (s): individual contract (r): for automobile accessories
chapter 1 outline preliminary user?s manual u1260ej3v1ud 23 1.4 pin configuration (top view) ? 64-pin plastic lqfp (10 10) ? 64-pin plastic lqfp (14 14) ? 64-pin plastic lqfp (12 12) ? 64-pin plastic tqfp (7 7) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p140/pcl/intp6 p141/buz/intp7 p00/ti000 p01/ti010/to00 p02/so11 note2 p03/si11 note2 p04/sck11 note2 p130 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p60/scl0 p61/sda0 p62/exscl0 p63 p33/ti51/to51/intp4 p77/kr7 p76/kr6 p75/kr5 p74/kr4 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p06/to01 note2 /ti011 note2 p05/ssi11 note2 /ti001 note2 p32/intp3/ocd1b note1 av ss av ref p10/sck10/txd0 p11/si10/rxd0 p12/so10 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p30/intp1 p53 p52 p51 p50 p31/intp2/ocd1a note1 p120/intp0/exlvi p43 p42 p41 p40 reset p124/xt2/exclks p123/xt1 flmd0 p122/x2/exclk/ocd0b note1 p121/x1/ocd0a note1 regc v ss ev ss v dd ev dd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 notes 1. pd78f0537d (product with on-chip debug function) only 2. pd78f0534, 78f0535, 78f053 6, 78f0537, 78f0537d only cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to v ss via a capacitor (0.47 f: target). 3. ani0/p20 to ani7/p27 ar e set in the analog input mode after release of reset.
chapter 1 outline preliminary user?s manual u17260ej3v1ud 24 ? 64-pin plastic flga (5 5) top view bottom view index mark 1 2 hg f e dc ba 3 4 5 6 7 8 h g f e d c b a pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 av ss c1 p24/ani4 e1 p130 g1 p141/buz/intp7 a2 av ref c2 p23/ani3 e2 p20/ani0 g2 p140/pcl/intp6 a3 p11/si10/rxd0 c3 p27/ani7 e3 p03/si11 note2 g3 p43 a4 p13/txd6 c4 p10/sck10/txd0 e4 p42 g4 reset a5 p16/toh1/intp5 c5 p17/ti50/to50 e5 p77/kr7 g5 regc a6 p53 c6 p30/intp1 e6 p33/ti51/to51/intp4 g6 v ss a7 p51 c7 p31/intp2/ ocd1a note1 e7 p74/kr4 g7 v dd a8 p32/intp3/ ocd1b note1 c8 p06 /to01 note2 / ti011 note2 e8 p76/kr6 g8 p61/sda0 b1 p25/ani5 d1 p21/ani1 f1 p01/ti010/to00 h1 p120/intp0/exlvi b2 p26/ani6 d2 p22/ani2 f2 p00/ti000 h2 p124/xt2/exclks b3 p12/so10 d3 p04/sck11 note2 f3 p02/so11 note2 h3 p123/xt1 b4 p15/toh0 d4 p72/kr2 f4 p41 h4 flmd0 b5 p14/rxd6 d5 p70/kr0 f5 p40 h5 p122/x2/exclk /ocd0b note1 b6 p52 d6 p71/kr1 f6 p60/scl0 h6 p121/x1/ocd0a note1 b7 p50 d7 p75/kr5 f7 p62/exscl0 h7 ev ss b8 p05/ssi11 note2 / ti001 note2 d8 p73/kr3 f8 p63 h8 ev dd notes 1. pd78f0537d (product with on-chip debug function) only 2. pd78f0534, 78f0535, 78f053 6, 78f0537, 78f0537d only cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to v ss via a capacitor (0.47 f: target). 3. ani0/p20 to ani7/p27 ar e set in the analog input mode after release of reset.
chapter 1 outline preliminary user?s manual u1260ej3v1ud 25 pin identification ani0 to ani7: analog input av ref : analog reference voltage av ss : analog ground buz: buzzer output ev dd : power supply for port ev ss : ground for port exclk: external clock input (main system clock) exclks: external clock input (subsystem clock) exlvi: external potential input for low-voltage detector exscl0: external serial clock input flmd0: flash programming mode intp0 to intp7: external interrupt input kr0 to kr7: key return ocd0a note1 , ocd0b note1 , ocd1a note1 , ocd1b note1 : on chip debug input/output p00 to p06: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p33: port 3 p40 to p43: port 4 p50 to p53: port 5 p60 to p63: port 6 p70 to p77: port 7 p120 to p124: port 12 p130: port 13 p140, p141: port 14 pcl: programmable clock output regc regulator capacitance reset: reset rxd0, rxd6: receive data sck10, sck11 note2 , scl0: serial clock input/output sda0: serial data input/output si10, si11 note2 : serial data input so10, so11 note2 : serial data output ssi11 note2 : serial interface chip select input ti000, ti010, ti001 note2 , ti011 note2 , ti50, ti51: timer input to00, to01 note2 , to50, to51, toh0, toh1: timer output txd0, txd6: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillat or (main system clock) xt1, xt2: crystal oscillator (subsystem clock) notes 1. pd78f0537d (product with on-chip debug function) only 2. pd78f0534, 78f0535, 78f053 6, 78f0537, 78f0537d only
chapter 1 outline preliminary user?s manual u17260ej3v1ud 26 1.5 78k0/kx2 series lineup 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 rom ram 30 pins 44 pins 48 pins 52 pins 64 pins 80 pins pd78f0527d note pd78f0537d note pd78f0547d note 128 kb 7 kb ? ? ? pd78f0527 pd78f0537 pd78f0547 96 kb 5 kb ? ? ? pd78f0526 pd78f0536 pd78f0546 pd78f0515d note 60 kb 3 kb ? ? pd78f0515 pd78f0525 pd78f0535 pd78f0545 48 kb 2 kb ? ? pd78f0514 pd78f0524 pd78f0534 pd78f0544 pd78f0503d note pd78f0513d note 32 kb 1 kb pd78f0503 pd78f0513 pd78f0513 pd78f0523 pd78f0533 ? 24 kb 1 kb pd78f0502 pd78f0512 pd78f0522 pd78f0532 ? 16 kb 768 b pd78f0501 pd78f0511 pd78f0521 pd78f0531 ? 8 kb 512 b pd78f0500 ? ? ? ? note product with on-chip debug function
chapter 1 outline preliminary user?s manual u1260ej3v1ud 27 the list of functions in the 78k 0/kx2 series is shown below. (1/2) 78k0/kb2 78k0/kc2 part number item 30/36 pins 44 pins 48 pins flash memory (kb) 8 16 24 32 16 24 32 16 24 32 48 60 ram (kb) 0.5 0.75 1 1 0.75 1 1 0.75 1 1 2 3 bank (flash memory) ? power supply voltage v dd = 1.8 to 5.5 v regulator provided minimum instruction execution time 0.1 s (20 mhz: v dd = 4.0 to 5.5 v)/0.2 s (10 mhz: v dd = 2.7 to 5.5 v)/ 0.4 s (5 mhz: v dd = 1.8 to 5.5 v) high-speed system 20 mhz: v dd = 4.0 to 5.5 v/10 mhz: v dd = 2.7 to 5.5 v/5 mhz: v dd = 1.8 to 5.5 v main internal high-speed oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v subsystem ? 32.768 khz (typ.): v dd = 1.8 to 5.5 v clock internal low-speed oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v total 23 37 41 port n-ch o.d. (6 v tolerance) 2 4 4 16 bits (tm0) 1 ch 8 bits (tm5) 2 ch 8 bits (tmh) 2 ch watch ? 1 ch timer wdt 1 ch 3-wire csi ? automatic transmit/ receive 3-wire csi ? uart/3-wire csi note 1 ch uart supporting lin- bus 1 ch serial interface i 2 c bus 1 ch 10-bit a/d 4 ch 8 ch external 6 7 8 interrupt internal 14 16 key interrupt ? 4 ch reset pin provided poc 1.59 v 0.15 v (rise time to 1.8 v: 3.6 ms (max.)) lvi the detection level of the supply voltage is selectable in 16 steps. reset wdt provided clock output/buzzer output ? clock output only multiplier/divider ? provided on-chip debug function pd78f0503d only pd78f0513d only pd78f0515d only operating ambient temperature ? 40 to +85 c ((t), (r), (s) products), ? 40 to +125 c ((t2) product) note select either of the functions of these alternate-function pins.
chapter 1 outline preliminary user?s manual u17260ej3v1ud 28 (2/2) 78k0/kd2 78k0/ke2 78k0/kf2 part number item 52 pins 64 pins 80 pins flash memory (kb) 16 24 32 48 60 96 128 16 24 32 48 60 96 128 48 60 96 128 ram (kb) 0.75 1 1 2 3 5 7 0.75 1 1 2 3 5 7 2 3 5 7 bank (flash memory) ? 4 6 ? 4 6 ? 4 6 power supply voltage v dd = 1.8 to 5.5 v regulator provided minimum instruction execution time 0.1 s (20 mhz: v dd = 4.0 to 5.5 v)/0.2 s (10 mhz: v dd = 2.7 to 5.5 v)/ 0.4 s (5 mhz: v dd = 1.8 to 5.5 v) high-speed system 20 mhz: v dd = 4.0 to 5.5 v/10 mhz: v dd = 2.7 to 5.5 v/5 mhz: v dd = 1.8 to 5.5 v main internal high-speed oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v subsystem 32.768 khz (typ.): v dd = 1.8 to 5.5 v clock internal low-speed oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v total 45 55 71 port n-ch o.d. (6 v tolerance) 4 4 4 16 bits (tm0) 1 ch 2 ch 8 bits (tm5) 2 ch 8 bits (tmh) 2 ch watch 1 ch timer wdt 1 ch 3-wire csi ? 1 ch automatic transmit/ receive 3-wire csi ? 1 ch uart/3-wire csi note 1 ch uart supporting lin- bus 1 ch serial interface i 2 c bus 1 ch 10-bit a/d 8 ch external 8 9 interrupt internal 16 19 20 key interrupt 8 ch reset pin provided poc 1.59 v 0.15 v (rise time to 1.8 v: 3.6 ms (max.)) lvi the detection level of the supply voltage is selectable in 16 steps. reset wdt provided clock output/buzzer output clock output only provided multiplier/divider ? provided ? provided on-chip debug function pd78f0527d only pd78f0537d only pd78f0547d only operating ambient temperature ? 40 to +85 c ((t), (r), (s) products), ? 40 to +125 c ((t2) product) note select either of the functions of these alternate-function pins.
chapter 1 outline preliminary user?s manual u1260ej3v1ud 29 1.6 block diagram port 0 p00 to p06 7 port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p33 4 port 4 port 5 v ss , ev ss flmd0 v dd , ev dd 8 port 6 p60 to p63 4 port 7 p70 to p77 port 12 p120 to p124 port 13 p130 8 p40 to p43 4 p50 to p53 4 port 14 p140, p141 2 buzzer output buz/p141 clock output control pcl/p140 ani0/p20 to ani7/p27 interrupt control 8 a/d converter av ref av ss intp1/p30 to intp4/p33 4 intp0/p120(linsel) serial interface iic0 exscl0/p62 sda0/p61 scl0/p60 intp5/p16 intp6/p140, intp7/p141 2 internal high-speed ram internal expansion ram note2 78k/0 cpu core flash memory bank note1 16-bit timer/ event counter 01 note2 to01 note2 /ti011 note2 /p06 ti001 note2 /p05 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 ti51/to51/p33 8-bit timer/ event counter 51 watch timer serial interface csi10 si10/p11 so10/p12 sck10/p10 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 (linsel) serial interface csi11 note2 si11 note2 /p03 so11 note2 /p02 sck11 note2 /p04 ssi11 note2 /p05 power on clear/ low voltage indicator poc/lvi control reset control key return 8 kr0/p70 to kr7/p77 exlvi/p120 system control reset x1/p121 x2/exclk/p122 internal high-speed oscillator xt1/p123 xt2/exclks/p124 multiplier& divider note2 on-chip debug note3 rxd6/p14 (linsel) rxd6/p14 (linsel) linsel 5 ocd0a note3 /x1, ocd1a note3 /p31 ocd0b note3 /x2, ocd1b note3 /p32 internal low-speed oscillator voltage regulator regc notes 1. available only in the pd78f0536, 78f0537, and 78f0537d. 2. available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d. 3. available only in the pd78f0537d.
chapter 1 outline preliminary user?s manual u17260ej3v1ud 30 1.7 outline of functions (1/2) item pd78f0531 pd78f0532 pd78f0533 pd78f0534 pd78f0535 pd78f0536 pd78f0537 pd78f0537d flash memory (self-programming supported) note 1 16 k 24 k 32 k 48 k 60 k 96 k 128 k memory bank note 2 ? 4 6 high-speed ram note 1 768 1 k internal memory (bytes) expansion ram note 1 ? 1 k 2 k 4 k 6 k memory space 64 kb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 1 to 20 mhz: v dd = 4.0 to 5.5 v, 1 to 10 mhz: v dd = 2.7 to 5.5 v, 1 to 5 mhz: v dd = 1.8 to 5.5 v main system clock (oscillation frequency) internal high-speed oscillation clock internal oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v subsystem clock (oscillation frequency) xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz (typ.): v dd = 1.8 to 5.5 v internal low-speed oscillation clock (for tmh1, wdt) internal oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) 0.1 s (high-speed system clock: @ f xh = 20 mhz operation) 0.25 s (typ.) (internal high-speed oscillation clock: @ f rh = 8 mhz (typ.) operation) minimum instruction execution time 122 s (subsystem clock: @ f sub = 32.768 khz operation) instruction set 8-bit operation, 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulate (set, reset, test, and b oolean operation) bcd adjust, etc. i/o ports total: 55 cmos i/o: 50 cmos output: 1 n-ch open-drain i/o (6 v tolerance): 4 timers 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels 8-bit timer: 2 channels watch timer: 1 channel watchdog timer: 1 channel 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels 8-bit timer: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 5 (pwm output: 4, ppg output: 1) 6 (pwm output: 4, ppg output: 2) clock output 156.25 khz, 312.5 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (peripheral hardware clock: @ f prs = 20 mhz operation) 32.768 khz (subsystem clock: @ f sub = 32.768 khz operation) buzzer output 2.44 khz, 4.88 khz, 9.77 khz, 19.54 khz (peripheral hardware clock: @ f prs = 20 mhz operation) a/d converter 10-bit resolution 8 channels (av ref = 2.3 to 5.5 v) notes 1. the internal flash memory capacity, internal hi gh-speed ram capacity, and internal expansion ram capacity can be changed using the internal memory size switching register (ims) and the internal expansion ram size switching register (ixs). 2. banks to be used can be changed using the bank select register (bank).
chapter 1 outline preliminary user?s manual u1260ej3v1ud 31 (2/2) item pd78f0531 pd78f0532 pd78f0533 pd78f0534 pd78f0535 pd78f0536 pd78f0537 pd78f0537d serial interface uart mode supporting lin- bus: 1 channel 3-wire serial i/o mode/uart mode note : 1 channel i 2 c bus mode: 1 channel uart mode supporting lin-bus: 1 channel 3-wire serial i/o mode/uart mode note : 1 channel 3-wire serial i/o mode: 1 channel i 2 c bus mode: 1 channel multiplier/divider ? 16 bits 16 bits = 32 bits (multiplication) 32 bits 16 bits = 32 bits remainder of 16 bits (division) internal 16 19 vectored interrupt sources external 9 key interrupt key interrupt (intkr) occurs by det ecting falling edge of key input pins (kr0 to kr7). reset reset using reset pin internal reset by watchdog timer internal reset by power-on-clear internal reset by low-voltage detector on-chip debug function ? provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c ((t), (r), (s) products) t a = ? 40 to +125 c ((t2) product) package 64-pin plastic lqfp (10 10) 64-pin plastic lqfp (14 14) 64-pin plastic lqfp (12 12) 64-pin plastic tqfp (7 7) 64-pin plastic flga (5 5) note select either of the functions of these alternate-function pins. caution the operating voltag e range may be changed after evaluation of the device. an outline of the timer is shown below. 16-bit timer/ event counters 00 and 01 note 1 8-bit timer/ event counters 50 and 51 8-bit timers h0 and h1 tm00 tm01 note 1 tm50 tm51 tmh0 tmh1 watch timer watchdog timer interval timer 1 channel 1 channel 1 c hannel 1 channel 1 channel 1 channel 1 c hannel note 2 ? external event counter 1 channel 1 channel 1 channel 1 channel ? ? ? ? ppg output 1 output 1 output ? ? ? ? ? ? pwm output ? ? 1 output 1 output 1 output 1 output ? ? pulse width measurement 2 inputs 2 inputs ? ? ? ? ? ? square-wave output 1 output 1 output 1 output 1 output 1 output 1 output ? ? carrier generator ? ? ? ? ? 1 output note 3 ? ? watch timer ? ? ? ? ? ? 1 channel note 2 ? function watchdog timer ? ? ? ? ? ? ? 1 channel interrupt source 2 2 1 1 1 1 1 ? notes 1. available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d. 2. in the watch timer, the watch timer function and interval timer function can be used simultaneously. 3. tm51 and tmh1 can be used in combinat ion as a carrier generator mode.
preliminary user?s manual u17260ej3v1ud 32 chapter 2 pin functions 2.1 pin function list there are three types of pi n i/o buffer power supplies: av ref , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p27 ev dd port pins other than p20 to p27 and p121 to p124 v dd ? p121 to p124 ? pins other than port (1) port functions (1/2) function name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note1 p03 si11 note1 p04 sck11 note1 p05 ti001 note1 / ssi11 note1 p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti011 note1 / to01 note1 p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti50/to50 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. analog input ani0 to ani7 p30 intp1 p31 intp2/ocd1a note2 p32 intp3/ocd1b note2 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti51/to51/intp4 notes 1. available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d. 2. pd78f0537d only
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 33 (1) port functions (2/2) function name i/o function after reset alternate function p40 to p43 i/o port 4. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p50 to p53 i/o port 5. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 sda0 p62 exscl0 p63 i/o port 6. 4-bit i/o port. output of p60 to p63 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port ? p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr0 to kr7 p120 intp0/exlvi p121 x1/ocd0a note p122 x2/exclk/ocd0b note p123 xt1 p124 i/o port 12. 5-bit i/o port. input/output can be specified in 1-bit units. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2/exclks p130 output port 13. 1-bit output-only port. output port ? p140 pcl/intp6 p141 i/o port 14. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port buz/intp7 note pd78f0537d only
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 34 (2) non-port functions (1/2) function name i/o function after reset alternate function intp0 p120/exlvi intp1 p30 intp2 p31/ocd1a note2 intp3 p32/ocd1b note2 intp4 p33/ti51/to51 intp5 p16/toh1 intp6 p140/pcl intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p141/buz si10 p11/rxd0 si11 note1 input serial data input to serial interface input port p03 so10 p12 so11 note1 output serial data output from serial interface input port p02 sda0 i/o serial data i/o for serial interface input port p61 sck10 p10/txd0 sck11 note1 p04 scl0 i/o clock input/output for serial interface input port p60 exscl0 input external clock input for serial interface. to input an external clock, input a clock of 6.4 mhz. input port p62 ssi11 note1 input chip select input for serial interface input port p05/ti001 rxd0 p11/si10 rxd6 input serial data input to asynchr onous serial interface input port p14 txd0 p10/sck10 txd6 output serial data output from asynch ronous serial interface input port p13 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti001 note1 external count clock input to 16-bit timer/event counter 01 capture trigger input to captur e registers (cr001, cr011) of 16-bit timer/event counter 01 p05/ssi11 note1 ti010 capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 p01/to00 ti011 note1 input capture trigger input to capture register (cr001) of 16-bit timer/event counter 01 input port p06/to01 note to00 16-bit timer/event counter 00 output p01/ti010 to01 note1 output 16-bit timer/event counter 01 output input port p06/ti011 note1 ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input port p33/to51/intp4 notes 1. pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only 2. pd78f0537d only
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 35 (2) non-port pins (2/2) function name i/o function after reset alternate function to50 8-bit timer/event counter 50 output p17/ti50 to51 8-bit timer/event counter 51 output p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input port p16/intp5 pcl output clock output (for trimming of high-speed system clock, subsystem clock) input port p140/intp6 buz output buzzer output input port p141/intp7 ani0 to ani7 input a/d converter analog input analog input p20 to p27 av ref input a/d converter reference voltage input and positive power supply for p20 to p27 and a/d converter ? ? av ss ? a/d converter ground potential. make the same potential as ev ss or v ss . ? ? kr0 to kr7 input key interrupt input input port p70 to p77 regc ? connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 f: target). ? ? reset input system reset input ? ? exlvi input potential input for external low-voltage detection input port p120/intp0 x1 input p121/ocd0a note x2 ? connecting resonator for main system clock input port p122/exclk/ ocd0b note exclk input external clock input for main system clock input port p122/x2/ ocd0b note xt1 input input port p123 xt2 ? connecting resonator fo r subsystem clock input port p124/exclks exclks input external clock input fo r subsystem clock input port p124/xt2 v dd ? positive power supply (p121 to p124 and except for ports) ? ? ev dd ? positive power supply for port s (except for p20 to p27 and p121 to p124) ? ? v ss ? ground potential (p121 to p124 and except for ports) ? ? ev ss ? ground potential for ports (except for p20 to p27 and p121 to p124) ? ? flmd0 ? flash memory programming mode setting ? ? ocd0a note p121/x1 ocd1a note input p31/intp2 ocd0b note p122/x2/exclk ocd1b note ? connection for on-chip debug mode setting pins ( pd78f0537d only) input port p32/intp3 note pd78f0537d only
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 36 2.2 description of pin functions 2.2.1 p00 to p06 (port 0) p00 to p06 function as a 7-bit i/o port. these pins also function as timer i/o, serial interface data i/o, clock i/o, and chip select input. the following operation modes can be specified in 1-bit units. (1) port mode p00 to p06 function as a 7-bit i/o port. p00 to p06 can be set to input or output port in 1-bit units using port mode register 0 (pm0). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p06 function as timer i/o, serial inte rface data i/o, clock i/o, and chip select input. (a) ti000, ti001 note these are the pins for inputting an external count clo ck to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the captur e registers (cr000, cr010 or cr001, cr011) of 16-bit timer/event counters 00 and 01. (b) ti010, ti011 note these are the pins for inputting a capt ure trigger signal to the capture re gister (cr000 or cr001) of 16-bit timer/event counters 00 and 01. (c) to00, to01 note these are timer output pins of 16- bit timer/event counters 00 and 01. (d) si11 note this is a serial data input pi n of serial interface csi11. (e) so11 note this is a serial data output pin of serial interface csi11. (f) sck11 note this is a serial clock i/o pin of serial interface csi11. (g) ssi11 note this is a chip select input pin of serial interface csi11. note pd78f0534, 78f0535, 78f0536, 78 f0537, and 78f0537d only
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 37 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. t hese pins also function as pins for ex ternal interrupt re quest input, serial interface data i/o, cl ock i/o, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output por t in 1-bit units using port mode register 1 (pm1). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interrupt request in put, serial interface data i/o, clock i/o, and timer i/o. (a) si10 this is a serial data input pi n of serial interface csi10. (b) so10 this is a serial data output pin of serial interface csi10. (c) sck10 this is a serial clock i/o pin of serial interface csi10. (d) rxd0 this is a serial data input pi n of serial interface uart0. (e) rxd6 this is a serial data input pi n of serial interface uart6. (f) txd0 this is a serial data output pin of serial interface uart0. (g) txd6 this is a serial data output pin of serial interface uart6. (h) ti50 this is the pin for inputting an external c ount clock to 8-bit timer/event counter 50. (i) to50 this is a timer output pin of 8-it timer/event counter 50. (j) toh0, toh1 these are the timer output pins of 8-bit timers h0 and h1. (k) intp5 this is an external interrupt request input pin for whic h the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 38 2.2.3 p20 to p27 (port 2) p20 to p27 function as an 8-bit i/o port. these pins also function as pins for a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit i/o port. p20 to p27 can be set to input or output por t in 1-bit units using port mode register 2 (pm2). (2) control mode p20 to p27 function as a/d converter analog input pins (ani0 to ani7). when using these pins as analog input pins, see (5) ani0/p20 to ani7/p27 in 13.6 cautions for a/d converter . caution ani0/p20 to ani 7/p27 are set in the analog in put mode after release of reset. 2.2.4 p30 to p33 (port 3) p30 to p33 function as a 4-bit i/o port. these pins also function as pins for external interrupt request input and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as a 4-bit i/o port. p30 to p33 can be set to input or output port in 1-bit units using port mode register 3 (pm3). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as external interrupt request input and timer i/o. (a) intp1 to intp4 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) ti51 this is an external count clock input pin to 8-bit timer/event counter 51. (c) to51 this is a timer output pin from 8-bit timer/event counter 51. caution in the pd78f0537d, be sure to pull the p31 pi n down before a reset release to prevent malfunction. remark only for the pd78f0537d, p31 and p32 can be used as on-chip debug mode setting pins (ocd1a, ocd1b) when the on-chip debug function is used. for how to connect an in-circuit emulator supporting on-chip debugging (qb-78k0mini), see chapter 27 on-chip debug function ( pd78f0537d only).
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 39 2.2.5 p40 to p43 (port 4) p40 to p43 function as a 4-bit i/o port. p40 to p43 can be set to input or output port in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (pu4). 2.2.6 p50 to p53 (port 5) p50 to p53 function as a 4-bit i/o port. p50 to p53 can be set to input or output port in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (pu5). 2.2.7 p60 to p63 (port 6) p60 to p63 function as a 4-bit i/o port. these pins also function as pins for serial in terface data i/o, clock i/o, and external clock input. the following operation modes can be specified in 1-bit units. (1) port mode p60 to p63 function as a 4-bit i/o port. p60 to p63 can be se t to input port or output port in 1-bit units using port mode register 6 (pm6). output of p60 to p63 is n-ch open-drain output (6 v tolerance). (2) control mode p60 to p63 function as serial interface dat a i/o, clock i/o, and external clock input. (a) sda0 this is a serial data i/o pin for serial interface iic0. (b) scl0 this is a serial clock i/o pi n for serial interface iic0. (c) exscl0 this is an external cl ock input pin to serial interface iic0. to input an external clock, input a clock of 6.4 mhz. 2.2.8 p70 to p77 (port 7) p70 to p77 function as an 8-bit i/o port. these pins also function as key interrupt input pins. the following operation modes can be specified in 1-bit units. (1) port mode p70 to p77 function as an 8-bit i/o port. p70 to p77 can be set to input or output por t in 1-bit units using port mode register 7 (pm7). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p77 function as key interrupt input pins. (a) kr0 to kr7 these are the key interrupt input pins
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 40 2.2.9 p120 to p124 (port 12) p120 to p124 function as a 5-bit i/o port. these pins also function as pins for extern al interrupt request input, potential input for external low-voltag e detection, connecting resonator for ma in system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. the following operation modes can be specified in 1-bit units. (1) port mode p120 to p124 function as a 5-bit i/o por t. p120 to p124 can be set to input or output port using port mode register 12 (pm12). only for p120, use of an on-chip pull-up resistor can be specifie d by pull-up resistor option register 12 (pu12). (2) control mode p120 to p124 function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and exter nal clock input for subsystem clock. (a) intp0 this functions as an external interrupt request inpu t (intp0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) exlvi this is a potential input pin for external low-voltage detection. (c) x1, x2 these are the pins for connecting a resonator for main system clock. (d) exclk this is an external clock inpu t pin for main system clock. (e) xt1, xt2 these are the pins for connecting a resonator for subsystem clock. (f) exclks this is an external clock in put pin for subsystem clock. remark only for the pd78f0537d, x1 and x2 can be used as on-chip debug mode setting pins (ocd0a, ocd0b) when the on-chip debug function is used . for how to connect an in-circuit emulator supporting on-chip debugging (qb-78k0mini), see chapter 27 on-chip debug function ( pd78f0537d only). 2.2.10 p130 (port 13) p130 functions as a 1-bit output-only port. remark when the device is reset, p130 outputs a low level. therefore, to output a high level from p130 before the device is reset, the output signa l of p130 can be used as a pseudo reset signal of the cpu (see the figure for remark in 5.2.10 port 13 ).
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 41 2.2.11 p140, p141 (port 14) p140 and p141 function as a 2-bit i/o port. these pins al so function as external interrupt request input, clock output, buzzer output. the following operation modes can be specified in 1-bit units. (1) port mode p140 and p141 function as a 2-bit i/o port. p140 and p141 c an be set to input or output port in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (pu14). (2) control mode p140 and p141 function as external interrupt request input, clock output, buzzer output. (a) intp6, intp7 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) pcl this is a clock output pin. (c) buz this is a buzzer output pin. 2.2.12 av ref this is the a/d converter reference voltage input pin and the positive power supply pin of p20 to p27 and a/d converter. when the a/d converter is not used, connect this pin directly to ev dd or v dd note . note make the av ref pin the same potential as the v dd pin when port 2 is used as a digital port. 2.2.13 av ss this is the a/d converter ground potenti al pin. even when the a/d converter is not used, always use this pin with the same potential as the v ss pin. 2.2.14 reset this is the active-low system reset input pin. 2.2.15 regc this is the pin for connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 f: target). regc v ss caution keep the wiring length as short as possible for the broken- line part in the above figure.
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 42 2.2.16 v dd and ev dd v dd is the positive power supply pin for other than p121 to p124 and ports. ev dd is the positive power supply pin for ports other than p20 to p27 and p121 to p124. 2.2.17 v ss and ev ss v ss is the ground potential pin for other than p121 to p124 and ports. ev ss is the ground potential pin for ports ot her than p20 to p27 and p121 to p124. 2.2.18 flmd0 this is a pin for setting flash memory programming mode. connect flmd0 to ev ss or v ss in the normal operation mode. in flash memory programming mode, connect this pin to the flash programmer.
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 43 2.3 pin i/o circuits and recommended connection of unused pins table 2-2 shows the types of pin i/o circuits and the recommended connections of unused pins. see figure 2-1 for the configuration of the i/o circuit of each type. table 2-2. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/ti000 p01/ti010/to00 5-ah p02/so11 note 1 5-ag p03/si11 note 1 p04/sck11 note 1 p05/ssi11 note 1 /ti001 note 1 p06/ti011 note 1 /to01 note 1 5-ag ( pd78f0531, 78f0532, 78f0533), 5-ah ( pd78f0534, 78f0535, 78f0536, 78f0537, 78f0537d) p10/sck10/txd0 p11/si10/rxd0 5-ah p12/so10 p13/txd6 5-ag p14/rxd6 5-ah p15/toh0 5-ag p16/toh1/intp5 p17/ti50/to50 5-ah input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/ani0 to p27/ani7 note 2 11-g connect to av ref or av ss . input: independently connect to ev dd or ev ss via a resistor. output: leave open. p30/intp1 p31/intp2 p32/intp3 p33/ti51/to51/intp4 5-ah p40 to p43 p50 to p53 5-ag input: independently connect to ev dd or ev ss via a resistor. output: leave open. p60/scl0 p61/sda0 p62/exscl0 13-ad p63 13-p input: connect to ev ss . output: leave this pin open at low-level output after clearing the output latch of the port to 0. p70/kr0 to p77/kr7 p120/intp0/exlvi 5-ah i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes 1. available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d. 2. p20/ani0 to p27/ani7 are set in the analog input mode after release of reset.
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 44 table 2-2. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p121/x1 note 1 p122/x2/exclk note 1 p123/xt1 note 1 p124/xt2/exclks note 1 37 i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. p130 3-c output leave open. p140/pcl/intp6 p141/buz/intp7 5-ah i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. reset 2 input ? flmd0 38 input connect to ev ss or v ss . av ref connect directly to ev dd or v dd note 2 . av ss ? ? connect directly to ev ss or v ss . notes 1. use recommended connecti on above in i/o port mode (see figure 6-2 format of clock operation mode select register (oscctl) ) when these pins are not used. 2. make the same potential as the v dd pin when port 2 is used as a digital port.
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 45 figure 2-1. pin i/o circuit list (1/2) type 2 type 5-ah schmitt-triggered input with hysteresis characteristics in pull-up enable data output disable input enable ev dd p-ch ev dd p-ch in/out n -ch ev ss type 3-c type 11-g ev dd p-ch n-ch data out ev ss data output disable av ref p-ch in/out n-ch p-ch n-ch series resistor string voltage comparator input enable + _ av ss av ss type 5-ag type 13-p pull-up enable data output disable input enable ev dd p-ch ev dd p-ch in/out n -ch ev ss data output disable input enable in/out n-ch ev ss
chapter 2 pin functions preliminary user?s manual u17260ej3v1ud 46 figure 2-1. pin i/o circuit list (2/2) type 13-ad type 38 data output disable input enable in/out n-ch ev ss input enable in type 37 data output disable input enable ev dd p-ch x1, xt1 n -ch ev ss reset data output disable input enable ev dd p-ch n -ch ev ss reset p-ch n-ch x2, xt2
preliminary user?s manual u17260ej3v1ud 47 chapter 3 cpu architecture 3.1 memory space products in the 78k0/ke2 can access a 64 kb memory sp ace. figures 3-1 to 3-8 show the memory maps. cautions 1. regardless of the inte rnal memory capacity, the initial val ues of the intern al memory size switching register (ims) and in ternal expansion ram size swit ching register (ixs) of all products in the 78k0/ke2 are fixed (ims = cf h, ixs = 0ch). therefore, set the value corresponding to each produc t as indicated below. 2. to set the memory size, set ims and then ixs. set the memory size so that the in ternal rom and internal expansion ram areas do not overlap. table 3-1. set values of internal memo ry size switching register (ims) and internal expansion ram si ze switching register (ixs) flash memory version (78k0/ke2) ims ixs rom capacity internal high-speed ram capacity internal expansion ram capacity pd78f0531 04h 16 kb 768 bytes pd78f0532 c6h 24 kb pd78f0533 c8h 0ch 32 kb ? pd78f0534 cch 0ah 48 kb 1 kb pd78f0535 cfh 0bh 60 kb 2 kb pd78f0536 cch note 04h 96 kb note 4 kb pd78f0537, 78f0537d cch note 00h 128 kb note 1 kb 6 kb note the pd78f0536, 78f0537, and 78f0537d have internal ro ms of 96 kb and 128 kb, respectively. however, the set value of ims of these devices is the same as thos e of the 48 kb product because memory banks are used. for how to set the memory banks, see 4.2 memory bank select register (bank) .
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 48 figure 3-1. memory map ( pd78f0531) special function registers (sfr) 256 x 8 bits internal high-speed ram 768 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 16384 x 8 bits program memory space data memory space vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1915 x 8 bits option byte area note1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note1 5 x 8 bits boot cluster 0 note2 boot cluster 1 ffffh ff00h feffh fee0h fedfh fc00h fbffh 4000h 3fffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h 3fffh 1fffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 security setting ).
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 49 figure 3-2. memory map ( pd78f0532) special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 24576 x 8 bits program memory space data memory space vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1915 x 8 bits option byte area note1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note1 5 x 8 bits boot cluster 0 note2 boot cluster 1 ffffh ff00h feffh fee0h fedfh fb00h faffh 6000h 5fffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h 5fffh 1fffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 security setting ).
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 50 figure 3-3. memory map ( pd78f0533) special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits program memory space data memory space vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1915 x 8 bits option byte area note1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note1 5 x 8 bits boot cluster 0 note2 boot cluster 1 ffffh ff00h feffh fee0h fedfh fb00h faffh 8000h 7fffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h 7fffh 1fffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 security setting ).
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 51 figure 3-4. memory map ( pd78f0534) internal expansion ram 1024 x 8 bits ram spcae in which instruction can be fetched program ram area special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 49152 x 8 bits program memory space data memory space vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1915 x 8 bits option byte area note1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note1 5 x 8 bits boot cluster 0 note2 boost cluster 1 reserved ffffh ff00h feffh fee0h fedfh fb00h faffh c000h bfffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h bfffh 1fffh f800h f7ffh f400h f3ffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 security setting ).
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 52 figure 3-5. memory map ( pd78f0535) internal expansion ram 2048 x 8 bits ram spcae in which instruction can be fetched program ram area special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 61440 x 8 bits program memory space data memory space vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1915 x 8 bits option byte area note1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note1 5 x 8 bits boot cluster 0 note2 boot cluster 1 ffffh ff00h feffh fee0h fedfh fb00h faffh f000h efffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h efffh 1fffh f800h f7ffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 security setting ).
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 53 figure 3-6. memory map ( pd78f0536) 0000h program memory space bank area common area internal expansion ram 4096 x 8 bits ram spcae in which instruction can be fetched program ram area special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits data memory space vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1915 x 8 bits option byte area note1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note1 5 x 8 bits boot cluster 0 note2 boot cluster 1 reserved ffffh ff00h feffh fee0h fedfh fb00h faffh c000h bfffh 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h 7fffh 1fffh f800h f7ffh e800h e7ffh 8000h 7fffh flash memory 16384 x 8 bits (memory bank 0) (memory bank 1) (memory bank 2) (memory bank 3) notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 security setting ).
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 54 figure 3-7. memory map ( pd78f0537) internal expansion ram 6144 x 8 bits ram spcae in which instruction can be fetched program ram area special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1915 x 8 bits option byte area note1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note1 5 x 8 bits boot cluster 0 note2 boot cluster 1 reserved ffffh ff00h feffh fee0h fedfh fb00h faffh c000h bfffh 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h 7fffh 1fffh f800h f7ffh e000h dfffh 8000h 7fffh flash memory 16384 x 8 bits (memory bank 0) (memory bank 1) (memory bank 2) (memory bank 3) data memory space program memory space 0000h (memory bank 5) (memory bank 4) bank area common area notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 security setting ).
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 55 figure 3-8. memory map ( pd78f0537d) internal expansion ram 6144 x 8 bits special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1905 x 8 bits option byte area note1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note1 5 x 8 bits boot cluster 0 note2 boot cluster 1 reserved ffffh ff00h feffh fee0h fedfh fb00h faffh c000h bfffh 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h 7fffh 1fffh f800h f7ffh e000h dfffh 8000h 7fffh flash memory 16384 x 8 bits (memory bank 0) (memory bank 1) (memory bank 2) (memory bank 3) 0000h (memory bank 5) (memory bank 4) data memory space ram spcae in which instruction can be fetched program ram area program memory space bank area common area 108fh 108eh 008fh 008eh on-chip debug security id setting area note1 10 x 8 bits on-chip debug security id setting area note1 10 x 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 security setting ).
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 56 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0/ke2 products incorporate internal rom (flash memory), as shown below. table 3-2. intern al rom capacity internal rom part number structure capacity pd78f0531 16384 8 bits (0000h to 3fffh) pd78f0532 24576 8 bits (0000h to 5fffh) pd78f0533 32768 8 bits (0000h to 7fffh) pd78f0534 49152 8 bits (0000h to bfffh) pd78f0535 61440 8 bits (0000h to efffh) pd78f0536 98304 8 bits (0000h to 7fffh (common area) + 8000h to bfffh (bank area) 4) pd78f0537, 78f0537d flash memory 131072 8 bits (0000h to 7fffh (common area) + 8000h to bfffh (bank area) 6) the internal program memory space is divided into the following areas. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vect or table area. the program start addresses for branch upon reset or generation of each interrupt reques t are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at ev en addresses and the higher 8 bits are stored at odd addresses.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 57 table 3-3. vector table vector table address interrupt source vector table address interrupt source 0000h reset input, poc, lvi, wdt 0020h inttm000 0004h intlvi 0022h inttm010 0006h intp0 0024h intad 0008h intp1 0026h intsr0 000ah intp2 0028h intwti 000ch intp3 002ah inttm51 000eh intp4 002ch intkr 0010h intp5 002eh intwt 0012h intsre6 0030h intp6 0014h intsr6 0032h intp7 0016h intst6 0034h intiic0/intdmu note 0018h intcsi10/intst0 0036h note intcsi11 note 001ah inttmh1 0038h note inttm001 note 001ch inttmh0 003ah note inttm011 note 001eh inttm50 003eh brk note available only in the pd78f0534, 78f0535, 78f05 36, 78f0537, and 78f0537d. (2) callt instruction table area the 64-byte area 0040h to 007fh can st ore the subroutine entry address of a 1-byte call instruction (callt). (3) option byte area a 5-byte area of 0080h to 0084h and 1080h to 1084h can be used as an option byte ar ea. set the option byte at 0080h to 0084h when the boot swap is not used, and at 0080h to 0084h and 1080h to 1084h when the boot swap is used. for details, see chapter 25 option byte . (4) callf instruction entry area the area 0800h to 0fffh can perform a direct subrout ine call with a 2-byte ca ll instruction (callf). (5) on-chip debug security id setting area ( pd78f0537d only) a 10-byte area of 0085h to 008eh and 1085h to 108eh can be used as an on-chip debug security id setting area. set the on-chip debug security id of 10 bytes at 0085h to 008eh when the boot swap is not used and at 0085h to 008eh and 1085h to 108eh when the boot swap is used. for details, see chapter 27 on-chip debug function ( pd78f0537d only) .
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 58 3.1.2 memory bank ( pd78f0536, 78f0537, and 78f0537d only) the 16 kb area 8000h to bfffh is assi gned to memory banks 0 to 3 in the pd78f0536, and assigned to memory banks 0 to 5 in the pd78f0537 and 78f0537d. the banks are selected by using a memory bank select register (bank). for details, see chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) ). cautions 1. instructions cannot be fe tched between different memory banks. 2. branch and access cannot be directly execute d between different memory banks. execute branch or access between different memory banks via the common area. 3. allocate interrupt ser vicing in the common area. 4. an instruction that extends from 7fffh to 8000h can only be executed in memory bank 0. 3.1.3 internal data memory space 78k0/ke2 products incorporate the following rams. (1) internal high-speed ram table 3-4. internal high-speed ram capacity part number internal high-speed ram pd78f0531 768 8 bits (fc00h to feffh) pd78f0532 pd78f0533 pd78f0534 pd78f0535 pd78f0536 pd78f0537, 78f0537d 1024 8 bits (fb00h to feffh) the 32-byte area fee0h to feffh is assigned to four g eneral-purpose register banks consisting of eight 8-bit registers per bank. this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 59 (2) internal expansion ram table 3-5. internal expansion ram capacity part number internal expansion ram pd78f0531 pd78f0532 pd78f0533 ? pd78f0534 1024 8 bits (f400h to f7ffh) pd78f0535 2048 8 bits (f000h to f7ffh) pd78f0536 4096 8 bits (e800h to f7ffh) pd78f0537, 78f0537d 6144 8 bits (e000h to f7ffh) the internal expansion ram can also be used as a normal data area similar to the internal high-speed ram, as well as a program area in which inst ructions can be written and executed. the internal expansion ram cannot be used as a stack memory. 3.1.4 special function register (sfr) area on-chip peripheral hard ware special function registers (sfrs) ar e allocated in the area ff00h to ffffh (see table 3-6 special function register list in 3.2.3 special func tion registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. 3.1.5 data memory addressing addressing refers to the method of specifying the address of the instruction to be ex ecuted next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executi on of instructions for the 78k0/ke2, based on operability and other consid erations. for areas containing dat a memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figures 3-9 to 3-15 show correspondence between data memory and addressing. for details of each addressing mode, see 3.4 operand address addressing .
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 60 figure 3-9. correspondence between data memory and addressing ( pd78f0531) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 768 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 16384 x 8 bits ffffh ff00h feffh fee0h fedfh fc00h fbffh 4000h 3fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 61 figure 3-10. correspondence between data memory and addressing ( pd78f0532) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 24576 x 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh 6000h 5fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 62 figure 3-11. correspondence between data memory and addressing ( pd78f0533) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh 8000h 7fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 63 figure 3-12. correspondence between data memory and addressing ( pd78f0534) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 49152 x 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh c000h bfffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing reserved f800h f7ffh f400h f3ffh internal expansion ram 1024 x 8 bits
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 64 figure 3-13. correspondence between data memory and addressing ( pd78f0535) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 61440 x 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing f800h f7ffh f000h efffh internal expansion ram 2048 x 8 bits
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 65 figure 3-14. correspondence between data memory and addressing ( pd78f0536) 16384 x 8 bits (memory bank 2) note sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh c000h bfffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing reserved f800h f7ffh e800h e7ffh internal expansion ram 4096 x 8 bits fa00h f9ffh 8000h 7fffh flash memory 16384 x 8 bits (memory bank 0) note 16384 x 8 bits (memory bank 3) note 16384 x 8 bits (memory bank 1) note fa20h fa1fh note to branch to or address a memory bank that is not se t by the memory bank select register (bank), change the setting of the memory bank by using bank.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 66 figure 3-15. correspondence between data memory and addressing ( pd78f0537, 78f0537d) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh c000h bfffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing reserved f800h f7ffh e000h dfffh internal expansion ram 6144 x 8 bits fa00h f9ffh 8000h 7fffh flash memory 16384 x 8 bits (memory bank 0) note 16384 x 8 bits (memory bank 2) note 16384 x 8 bits (memory bank 3) note 16384 x 8 bits (memory bank 1) note 16384 x 8 bits (memory bank 4) note 16384 x 8 bits (memory bank 5) note fa20h fa1fh note to branch to or address a memory bank that is not se t by the memory bank select register (bank), change the setting of the memory bank by using bank.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 67 3.2 processor registers the 78k0/ke2 products incorporate t he following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit regist er that holds the address information of the next program to be executed. in normal operation, pc is automatically incremented acco rding to the number of byte s of the instruction to be fetched. when a branch instruction is execut ed, immediate data and regi ster contents are set. reset signal generation sets the reset vector table va lues at addresses 0000h and 0001h to the program counter. figure 3-16. format of program counter 15 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents are stored in the stack area upon interr upt request generation or push psw instruction execution and are re stored upon execution of the retb , reti and pop psw instructions. reset signal generation sets psw to 02h. figure 3-17. format of program status word ie z rbs1 ac rbs0 isp cy 70 0 psw (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and all maskable interrupt requests are disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgement is controlled with an in-service priority flag (isp), an in terrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executi on or interrupt acknowledgement and is set (1) upon ei instruction execution.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 68 (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates t he register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bi t 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable ma skable vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified by a priority specification flag register (pr0l, pr0h, pr1l, pr1h) (see 19.3 (3) priority specifi cation flag registers (pr0l, pr0h, pr1l, pr1h) ) can not be acknowledged. actual request acknowledgement is controll ed by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of t he memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-18. format of stack pointer 15 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-19 and 3-20. caution since reset signal genera tion makes the sp contents undefined, be sure to initialize the sp before using the stack.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 69 figure 3-19. data to be saved to stack memory (a) push rp instruction (when sp = fee0h) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) call, callf, callt instructions (when sp = fee0h) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) interrupt, brk instruct ions (when sp = fee0h) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 70 figure 3-20. data to be restored from stack memory (a) pop rp instruction (when sp = fedeh) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) ret instruction (when sp = fedeh) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) reti, retb instructions (when sp = feddh) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 71 3.2.2 general-purpose registers general-purpose registers are mapp ed at particular addresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 bank s, each bank consisting of eight 8-bit r egisters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit r egisters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instructi on execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program ca n be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-21. configuration of general-purpose registers (a) function name register bank 0 register bank 1 register bank 2 register bank 3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h (b) absolute name register bank 0 register bank 1 register bank 2 register bank 3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 72 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special f unction register has a special function. sfrs are allocated to the ff00h to ffffh area. special function registers can be manipulated like general -purpose registers, using o peration, transfer, and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the spec ial function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler fo r the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler fo r the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-6 gives a list of the special f unction registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a special function regist er. it is a reserved word in the ra78k0, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0. when using the ra78k0, id78k0-qb, and sm+ for 78k0/kx2, symbols can be wr itten as an instruction operand. ? r/w indicates whether the corresponding special f unction register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 73 table 3-6. special function register list (1/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port register 0 p0 r/w ? 00h ff01h port register 1 p1 r/w ? 00h ff02h port register 2 p2 r/w ? 00h ff03h port register 3 p3 r/w ? 00h ff04h port register 4 p4 r/w ? 00h ff05h port register 5 p5 r/w ? 00h ff06h port register 6 p6 r/w ? 00h ff07h port register 7 p7 r/w ? 00h ff08h 10-bit a/d conversion result register adcr r ? ? 0000h ff09h 8-bit a/d conversion result register adcrh r ? ? 00h ff0ah receive buffer register 6 rxb6 r ? ? ffh ff0bh transmit buffer register 6 txb6 r/w ? ? ffh ff0ch port register 12 p12 r/w ? 00h ff0dh port register 13 p13 r/w ? 00h ff0eh port register 14 p14 r/w ? 00h ff0fh serial i/o shift register 10 sio10 r ? ? 00h ff10h ff11h 16-bit timer counter 00 tm00 r ? ? 0000h ff12h ff13h 16-bit timer capture/compare register 000 cr000 r/w ? ? 0000h ff14h ff15h 16-bit timer capture/compare register 010 cr010 r/w ? ? 0000h ff16h 8-bit timer counter 50 tm50 r ? ? 00h ff17h 8-bit timer compare register 50 cr50 r/w ? ? 00h ff18h 8-bit timer h compare register 00 cmp00 r/w ? ? 00h ff19h 8-bit timer h compare register 10 cmp10 r/w ? ? 00h ff1ah 8-bit timer h compare register 01 cmp01 r/w ? ? 00h ff1bh 8-bit timer h compare register 11 cmp11 r/w ? ? 00h ff1fh 8-bit timer counter 51 tm51 r ? ? 00h ff20h port mode register 0 pm0 r/w ? ffh ff21h port mode register 1 pm1 r/w ? ffh ff22h port mode register 2 pm2 r/w ? ffh ff23h port mode register 3 pm3 r/w ? ffh ff24h port mode register 4 pm4 r/w ? ffh ff25h port mode register 5 pm5 r/w ? ffh ff26h port mode register 6 pm6 r/w ? ffh ff27h port mode register 7 pm7 r/w ? ffh ff28h a/d converter mode register adm r/w ? 00h ff29h analog input channel specification register ads r/w ? 00h ff2ch port mode register 12 pm12 r/w ? ffh ff2eh port mode register 14 pm14 r/w ? ffh ff2fh a/d port configuration register adpc r/w ? 00h
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 74 table 3-6. special function register list (2/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff30h pull-up resistor option register 0 pu0 r/w ? 00h ff31h pull-up resistor option register 1 pu1 r/w ? 00h ff33h pull-up resistor option register 3 pu3 r/w ? 00h ff34h pull-up resistor option register 4 pu4 r/w ? 00h ff35h pull-up resistor option register 5 pu5 r/w ? 00h ff37h pull-up resistor option register 7 pu7 r/w ? 00h ff3ch pull-up resistor option register 12 pu12 r/w ? 00h ff3eh pull-up resistor option register 14 pu14 r/w ? 00h ff40h clock output selection register cks r/w ? 00h ff41h 8-bit timer compare register 51 cr51 r/w ? ? 00h ff43h 8-bit timer mode control register 51 tmc51 r/w ? 00h ff48h external interrupt risi ng edge enable register egp r/w ? 00h ff49h external interrupt fa lling edge enable register egn r/w ? 00h ff4ah serial i/o shift register 11 note sio11 r ? ? 00h ff4ch transmit buffer register 11 note sotb11 r/w ? ? 00h ff4fh input switch control register isc r/w ? 00h ff50h asynchronous serial interface operation mode register 6 asim6 r/w ? 01h ff53h asynchronous serial interface reception error status register 6 asis6 r ? ? 00h ff55h asynchronous serial interface transmission status register 6 asif6 r ? ? 00h ff56h clock selection register 6 cksr6 r/w ? ? 00h ff57h baud rate generator control register 6 brgc6 r/w ? ? ffh ff58h asynchronous serial interface control register 6 asicl6 r/w ? 16h ff60h sdr0l ? 00h ff61h remainder data register 0 note sdr0 sdr0h r ? 00h ff62h mda0ll ? 00h ff63h mda0l mda0lh r/w ? 00h ff64h mda0hl ? 00h ff65h multiplication/division data register a0 note mda0h mda0hh r/w ? 00h ff66h mdb0l ? 00h ff67h multiplication/division data register b0 note mdb0 mdb0h r/w ? 00h ff68h multiplier/divider control register 0 note dmuc0 r/w ? 00h ff69h 8-bit timer h mode register 0 tmhmd0 r/w ? 00h ff6ah timer clock selection register 50 tcl50 r/w ? 00h ff6bh 8-bit timer mode control register 50 tmc50 r/w ? 00h ff6ch 8-bit timer h mode register 1 tmhmd1 r/w ? 00h ff6dh 8-bit timer h carrier control register 1 tmcyc1 r/w ? 00h ff6eh key return mode register krm r/w ? 00h ff6fh watch timer operation mode register wtm r/w ? 00h note available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 75 table 3-6. special function register list (3/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff70h asynchronous serial interface operation mode register 0 asim0 r/w ? 01h ff71h baud rate generator control register 0 brgc0 r/w ? ? 1fh ff72h receive buffer register 0 rxb0 r ? ? ffh ff73h asynchronous serial interface reception error status register 0 asis0 r ? ? 00h ff74h transmit shift register 0 txs0 w ? ? ffh ff80h serial operation mode register 10 csim10 r/w ? 00h ff81h serial clock select ion register 10 csic10 r/w ? 00h ff84h transmit buffer register 10 sotb10 r/w ? ? 00h ff88h serial operation mode register 11 note 1 csim11 r/w ? 00h ff89h serial clock selection register 11 note 1 csic11 r/w ? 00h ff8ch timer clock selection register 51 tcl51 r/w ? 00h ff99h watchdog timer enable register wdte r/w ? ? note 2 1ah/9ah ff9fh clock operation mode select register oscctl r/w ? 00h ffa0h internal oscillation mode register rcm r/w ? 80h note 3 ffa1h main clock mode register mcm r/w ? 00h ffa2h main osc control register moc r/w ? 80h ffa3h oscillation stabilization time counter status register ostc r ? 00h ffa4h oscillation stabilization time select register osts r/w ? ? 05h ffa5h iic shift register 0 iic0 r/w ? ? 00h ffa6h iic control register 0 iicc0 r/w ? 00h ffa7h slave address register 0 sva0 r/w ? ? 00h ffa8h iic clock selection register 0 iiccl0 r/w ? 00h ffa9h iic function expansion register 0 iicx0 r/w ? 00h ffaah iic status register 0 iics0 r ? 00h ffabh iic flag register 0 iicf0 r/w ? 00h ffach reset control flag register resf r ? ? 00h note 4 ffb0h ffb1h 16-bit timer counter 01 note 1 tm01 r ? ? 0000h ffb2h ffb3h 16-bit timer capture/compare register 001 note 1 cr001 r/w ? ? 0000h ffb4h ffb5h 16-bit timer capture/compare register 011 note 1 cr011 r/w ? ? 0000h ffb6h 16-bit timer mode control register 01 note 1 tmc01 r/w ? 00h ffb7h prescaler mode register 01 note 1 prm01 r/w ? 00h ffb8h capture/compare control register 01 note 1 crc01 r/w ? 00h ffb9h 16-bit timer output control register 01 note 1 toc01 r/w ? 00h ffbah 16-bit timer mode control register 00 tmc00 r/w ? 00h notes 1. available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d. 2. the reset value of wdte is determined by setting of option byte. 3. the value of this register is 00h immediately after a reset release but automatically changes to 80h after internal high-speed oscillator has been stabilized. 4. the reset value of resf varies depending on the reset source.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 76 table 3-6. special function register list (4/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffbbh prescaler mode register 00 prm00 r/w ? 00h ffbch capture/compare control register 00 crc00 r/w ? 00h ffbdh 16-bit timer output control register 00 toc00 r/w ? 00h ffbeh low-voltage detection register lvim r/w ? 00h note 1 ffbfh low-voltage detection level selection register lvis r/w ? 00h note 1 ffe0h interrupt request flag register 0l if0 if0l r/w 00h ffe1h interrupt request flag register 0h if0h r/w 00h ffe2h interrupt request flag register 1l if1 if1l r/w 00h ffe3h interrupt request flag register 1h if1h r/w 00h ffe4h interrupt mask flag register 0l mk0 mk0l r/w ffh ffe5h interrupt mask flag register 0h mk0h r/w ffh ffe6h interrupt mask flag register 1l mk1 mk1l r/w ffh ffe7h interrupt mask flag register 1h mk1h r/w ffh ffe8h priority specification flag register 0l pr0 pr0l r/w ffh ffe9h priority specification flag register 0h pr0h r/w ffh ffeah priority specification flag register 1l pr1 pr1l r/w ffh ffebh priority specification flag register 1h pr1h r/w ffh fff0h internal memory size switching register note 2 ims r/w ? ? cfh fff3h memory bank select register bank r/w ? ? 00h fff4h internal expansion ram size switching register note 2 ixs r/w ? ? 0ch fffbh processor clock control register pcc r/w ? 01h notes 1. the reset values of lvim and lvis vary depending on the reset source. 2. regardless of the internal memory capacity, the init ial values of the internal memory size switching register (ims) and internal expansion ram size switchi ng register (ixs) of all products in the 78k0/ke2 are fixed (ims = cfh, ixs = 0ch). therefore, set the value corresponding to each product as indicated below. flash memory version (78k0/ke2) ims ixs rom capacity internal high-speed ram capacity internal expansion ram capacity pd78f0531 04h 16 kb 768 bytes pd78f0532 c6h 24 kb pd78f0533 c8h 0ch 32 kb ? pd78f0534 cch 0ah 48 kb 1 kb pd78f0535 cfh 08h 60 kb 2 kb pd78f0536 cch 04h 48 kb 4 kb pd78f0537, 78f0537d cch 00h 48 kb 1 kb 6 kb
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 77 3.3 instruction address addressing an instruction address is determined by contents of the program counter (pc) and memory bank select register (bank), and is normally incremented (+1 for each byte) aut omatically according to the number of bytes of an instruction to be fetched each time another instruction is ex ecuted. when a branch instruct ion is executed, the branch destination information is set to pc and branched by the followi ng addressing (for details of instructions, refer to the 78k/0 series instructions user?s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displ acement value: jdisp8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of relati ve branching from the start address of the following instruction to the ? 128 to +127 range. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ...
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 78 3.3.2 immediate addressing [function] immediate data in the instruction word is tran sferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructi ons can be branched to the entire me mory space. however, before branching to a memory bank that is not set by the me mory bank select register (bank), change the setting of the memory bank by using bank. the callf !addr11 instruction is br anched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 79 3.3.3 table indirect addressing [function] table contents (branch destinat ion address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation co de are transferred to the progr am counter (pc) and branched. this function is carried out when the ca llt [addr5] instruction is executed. this instruction references the address stored in the me mory table from 40h to 7fh, and allows branching to the entire memory space. however, before branching to a memory bank t hat is not set by the memory bank select register (bank), change the setting of the memory bank by using bank. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 operation code 3.3.4 register addressing [function] register pair (ax) contents to be spec ified with an instruction word are trans ferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 80 3.4 operand address addressing the following methods are available to specify the r egister and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/ke2 instruction words, the followi ng instructions employ implied addressing. instruction register to be s pecified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric va lues that become decimal correction targets ror4/rol4 a register for storage of di git data that undergoes digit rotation [operand format] because implied addressing can be automatically determined with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the pr oduct of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 81 3.4.2 register addressing [function] the general-purpose register to be specified is accesse d as an operand with the regi ster bank select flags (rbs0 to rbs1) and the register s pecify codes of an operation code. register addressing is carried out when an instruction wi th the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 0 1 1 0 0 0 1 0 register specify code incw de; when selecting de register pair as rp operation code 1 0 0 0 0 1 0 0 register specify code
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 82 3.4.3 direct addressing [function] the memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. this addressing can be carried out for all of the memo ry spaces. however, before addressing a memory bank that is not set by the memory bank select register (bank), change the setting of the memory bank by using bank. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op c ode 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 83 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and compare and capture regi sters of the timer/event counter are mapped in this area, allowing sfrs to be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see the [illustration] shown below. [operand format] identifier description saddr immediate data that indicate label or fe20h to ff1fh saddrp immediate data that indicate label or fe20h to ff1fh (even address only) [description example] lb1 equ 0fe30h ; defines fe30h by lb1. : mov lb1, a ; when lb1 indicates fe30h of the saddr ar ea and the value of register a is transferred to that address operation code 1 1 1 1 0 0 1 0 op code 0 0 1 1 0 0 0 0 30h (saddr-offset) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 84 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffff h. however, the sfrs mapped at ff00h to ff1fh can be ac cessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special func tion register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 1 1110110 op c ode 0 0100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 85 3.4.6 register indirect addressing [function] register pair contents specified by a register pair spec ify code in an instruction word and by a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory. this addressing can be carried out for all of the memo ry spaces. however, before addressing a memory bank that is not set by the memory bank select register (bank), change the setting of the memory bank by using bank. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 1 0 0 0 0 1 0 1 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 86 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the content s of the base register, that is , the hl register pair in the register bank specifie d by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offs et data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all of the memo ry spaces. however, before addressing a memory bank that is not set by the memory bank select register (bank), change the setting of the memory bank by using bank. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 [illustration] 16 0 8 h 7 l 0 7 7 0 a hl the contents of the memory addressed are transferred. memory + 10
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 87 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is perform ed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all of the memo ry spaces. however, before addressing a memory bank that is not set by the memory bank select register (bank), change the setting of the memory bank by using bank. [operand format] identifier description ? [hl + b], [hl + c] [description example] mov a, [hl +b]; when selecting b register operation code 1 0 1 0 1 0 1 1 [illustration] 16 0 h 7 8 l 0 7 b + 0 7 7 0 a hl the contents of the memory addressed are transferred. memory
chapter 3 cpu architecture preliminary user?s manual u17260ej3v1ud 88 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is sa ved/reset upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be accessed. [description example] push de; when saving de register operation code 10110101 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh
preliminary user?s manual u17260ej3v1ud 89 chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) 4.1 memory bank the pd78f0536, 78f0537, and 78f0537d implement a rom capacity of 96 kb or 128 kb by selecting a memory bank from a memory space of 8000h to bfffh. the pd78f0536 has memory banks 0 to 3, and the pd78f0537 and 78f0537d have memory banks 0 to 5, as shown below. the memory banks are selected by using a memory bank select register (bank). figure 4-1. internal rom (f lash memory) configuration (a) pd78f0536 8000h 7fffh 0000h flash memory 32768 8 bits bfffh flash memory 16384 8 bits (memory bank 0) (memory bank 1) (memory bank 2) common area bank area (memory bank 3) (b) pd78f0537, 78f0537d 8000h 7fffh 0000h flash memory 32768 8 bits bfffh flash memory 16384 8 bits (memory bank 0) (memory bank 1) common area bank area (memory bank 3) (memory bank 4) (memory bank 5) (memory bank 2)
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 90 4.2 memory bank select register (bank) the memory bank select register (bank) is used to select a memory bank to be used. bank can be set by an 8-bit memory manipulation instruction. reset signal generation clears bank to 00h. figure 4-2. format of memory bank select register (bank) address: fff3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 bank 0 0 0 0 0 bank2 bank1 bank0 bank setting bank2 bank1 bank0 pd78f0536 pd78f0537, 78f0537d 0 0 0 common area (32 k) + memory bank 0 (16 k) 0 0 1 common area (32 k) + memory bank 1 (16 k) 0 1 0 common area (32 k) + memory bank 2 (16 k) 0 1 1 common area (32 k) + memory bank 3 (16 k) 1 0 0 common area (32 k) + memory bank 4 (16 k) 1 0 1 setting prohibited common area (32 k) + memory bank 5 (16 k) other than above setting prohibited caution be sure to change the value of the bank register in the common area (0000h to 7fffh). if the value of the bank register is changed in the bank area (8000h to bfffh), an inadvertent program loop occurs in the cpu. therefore, never change the value of the bank register in the bank area.
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 91 4.3 selecting memory bank the memory bank selected by the memory bank select re gister (bank) is reflected on the bank area and can be addressed. therefore, to access a memory bank different fr om the one currently selected , that memory bank must be selected by using the bank register. the value of the bank register must not be changed in the bank area (8000h to bfffh). therefore, to change the memory bank, branch an instruction to the common area (0000h to 7fffh) and c hange the value of the bank register in that area. cautions 1. instructions cannot be fe tched between different memory banks. 2. branching and accessing cannot be directly executed between differ ent memory banks. execute branching or accessing between diff erent memory banks via the common area. 3. allocate interrupt ser vicing in the common area. 4. an instruction that extends from 7fffh to 8000h can only be executed in memory bank 0. 4.3.1 referencing valu es between memory banks values cannot be directly referenced from one memory bank to another. to access another memory bank from one memory bank, branch once to the common area (0000h to 7fffh), change the setting of the bank register there, and then reference a value. memory bank m common area bank area memory bank n referencing value common area bank area referencing value memory bank m memory bank n
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 92 ? software example (to store a value to be referenced in register a) remark in the software example above, the x register is destructed. ramd dseg saddr r_bnka: ds 2 ; secures ram for specifyi ng an address at the reference destination. r_bnkn: ds 1 ; secures ram for specifying a me mory bank number at the reference destination. r_bnkrn: ds 1 ; secures ram for saving a me mory bank number at the reference source. ; mov r_bnkn,#banknum data1 ; stores the memo ry bank number at the reference destination. movw r_bnka,#data1 ; stores the address at the reference destination. call !bnkrd ; calls a subroutine for referencing between memory banks. : : bnkc cseg at 7000h bnkrd: ; subroutine for referencing between memory banks. push hl ; saves the contents of register hl. mov a,r_bnkn ; xch a,bank ; swaps the memory bank number at the reference source for that at the reference ; destination mov r_bnkrn,a ; saves the memory bank number at the reference source. movw ax,r_bnka ; xchw hl,ax ; specifies the address at the reference destination. mov a,[hl] ; reads the target value. xch a,r_bnkrn ; acquires the memory bank number at the reference source. mov bank,a ; specifies the memory bank number at the reference source. mov a,r_bnkrn ; pop hl ; restores t he contents of register hl. ret ; return data cseg bank3 data1: db 0aah end
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 93 4.3.2 branching instruct ion between memory banks instructions cannot branch directly from one memory bank to another. to branch an instruction from one memory bank to another , branch once to the comm on area (0000h to 7fffh), change the setting of the bank r egister there, and then execute the branch instruction again. memory bank m common area bank area memory bank n instruction branch common area bank area instruction branch memory bank m memory bank n
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 94 ? software example remark in the software example above, the ax register is destructed. ramd dseg saddr r_bnka: ds 2 ; secures ram for specifyi ng a memory bank at the branch destination. r_bnkn: ds 1 ; secures ram for specifying a memory bank number at the branch destination. mov r_bnkn,#banknum test ; stores the memory bank number at the branch destination in ram. movw r_bnka,#test ; stores the addr ess at the branch destination in ram. br !bnkbr ; branches to inte r-memory bank branch processing. : : bnkc cseg at 7000h ; bnkbr: mov a,r_bnkn ; mov bank,a ; specifies the memory bank number at the branch destination. movw ax,r_bnka ; specifies the address at the branch destination. br ax ; branch bn3 cseg bank3 test: mov ??? : : end
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 95 4.3.3 subroutine call between memory banks subroutines cannot be directly called between memory banks. to call a subroutine between memory banks, branch once to the common ar ea (0000h to 7fffh), specify the memory bank at the calling destination by using the bank register there, execut e the call instruction, and branch to the call destination by that instruction. at this time, save the current value of the bank register to ram. restore the value of the bank register before executing the re t instruction. memory bank m common area bank area memory bank n br instruction common area bank area call instruction memory bank m memory bank n call inst- ruction call instruction change bank and save memory bank number at calling source. ret instruction ret instruction
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 96 ? software example remark in the software example above, the ax register is des tructed. multiplexed processing is not supported. ramd dseg saddr r_bnka: ds 2 ; secures ram for specif ying an address at the calling destination. r_bnkn: ds 1 ; secures ram for specifying a memory bank number at the calling destination. r_bnkrn: ds 1 ; secures ram for saving a memory bank number at the calling source. mov r_bnkn,#banknum test ; store the memory bank number at the calling destination in ram. movw r_bnka,#test ; stores the addr ess at the calling destination in ram. call !bnkcal ; branches to an inter-memory bank calling processing routine. : : bnkc cseg at 7000h bnkcal: ; inter-memory bank calling processing routine mov a,r_bnkn ; acquires the memory bank number at the calling destination. xch a,bank ; changes the bank and acquires the memory bank number at the calling source. mov r_bnkrn,a ; saves the memory bank number at the calling source to ram. call !bnkcals ; calls a subroutine to branch to the calling destination. xch a,r_bnkrn ; mov bank,a ; specifies the memory bank number at the calling source. ret ; returns to the calling source. bnkcals: movw ax,r_bnka ; specifies the address at the calling destination. br ax ; branches to the calling destination. bn3 cseg bank3 test: ; mov ??? : : ret end
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 97 4.3.4 instruction branch to bank area by interrupt when an interrupt occurs, instructions can branch to the me mory bank specified by the bank register by using the vector table, but it is difficult to identif y the bank register when the interrupt occurs. therefore, specify the branch destinatio n address specified by the vector table in the common area (0000h to 7fffh), specify the memory bank at the branch destinati on by using the bank register in the common area, and execute the call instruction. at this time, save the ba nk register value before the change to ram, and restore the value of the bank register before executing the reti instruction. remark allocate interrupt servicing that requires a quick response in the common area. memory bank m common area bank area memory bank n instruction branch save the original memory bank number. specify the address and memory bank at the destination, and execute the call instruction. vector table ? software example (when using interrupt request of 16-bit timer/event counter 00) vctbl cseg at 0020h dw bnkitm000 ; specifies an address at the timer interrupt destination. ramd dseg saddr r_bnkrn: ds 1 ; secures ram for saving the memory bank number before the interrupt occurs. bnkc cseg at 7000h bnkitm000: ; inter-memory ban k interrupt servicing routine push ax ; saves the contents of the ax register. mov a,bank mov r_bnkrn,a ; saves the memory bank number before the interrupt to ram. mov bank,#banknum test ; specifies the memory bank number of the interrupt routine. call !test ; calls the interrupt routine. mov a,r_bnkrn ; restores the memory bank number before the interrupt. mov bank,a pop ax ; restores the contents of the ax register. reti bn3 cseg bank3 test: ; interrupt servicing routine mov ??? : : ret end
chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 98 remark note the following points to use the memory bank select function efficiently. ? allocate a routine that is used often in the common area. ? if a value that is planned to be referenced is placed in ram, it can be referenced from all of the areas. ? if the reference destination and the branch destinati on of the routine placed in a memory bank are placed in the same memory bank, then the code size and processing are more efficient. ? allocate interrupt servicing that requires a quick response in the common area.
preliminary user?s manual u17260ej3v1ud 99 chapter 5 port functions 5.1 port functions there are three types of pi n i/o buffer power supplies: av ref , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 5-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p27 ev dd port pins other than p20 to p27 and p121 to p124 v dd ? p121 to p124 ? non-port pins 78k0/ke2 products are provided with the ports shown in fi gure 5-1, which enable vari ety of control operations. the functions of each port are shown in table 5-2. in addition to the func tion as digital i/o ports, these ports have several alternate f unctions. for details of the alternate functions, see chapter 2 pin functions . figure 5-1. port types port 2 p20 p27 port 3 p30 p33 port 5 p50 p53 port 0 p00 p06 port 1 p10 p17 port 4 p40 p43 port 6 p60 p63 port 7 p70 p77 p120 port 12 port 14 p140 p141 p130 port 13 p124
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 100 table 5-2. port functions (1/2) pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note1 p03 si11 note1 p04 sck11 note1 p05 ssi11 note1 /ti001 note1 p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti011 note1 /to01 note1 p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti50/to50 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. analog input ani0 to ani7 p30 intp1 p31 intp2/ocd1a note2 p32 intp3/ocd1b note2 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port intp4/ti51/to51 p40 to p43 i/o port 4. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p50 to p53 i/o port 5. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 sda0 p62 exscl0 p63 i/o port 6. 4-bit i/o port (n-ch open drain). input/output can be specified in 1-bit units. input port ? p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr0 to kr7 notes 1. available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d. 2. pd78f0537d only
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 101 table 5-2. port functions (2/2) function name i/o function after reset alternate function p120 intp0/exlvi p121 x1/ocd0a note p122 x2/exclk/ocd0b note p123 xt1 p124 i/o port 12. 5-bit i/o port. input/output can be specified in 1-bit units. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2/exclks p130 output port 13. 1-bit output-only port. output port ? p140 pcl/intp6 p141 i/o port 14. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port buz/intp7 note pd78f0537d only 5.2 port configuration ports include the following hardware. table 5-3. port configuration item configuration control registers port mode register (pm0 to pm7, pm12, pm14) port register (p0 to p7, p12 to p14) pull-up resistor option register (pu0, pu1, pu3 to pu7, pu12, pu14) a/d port configuration register (adpc) port total: 55 (cmos i/o: 50, cmos output: 1, n-ch open drain i/o: 4) pull-up resistor total: 38
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 102 5.2.1 port 0 port 0 is a 7-bit i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p06 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o, serial in terface data i/o, clock i/o, and chip select input. reset signal generation sets port 0 to input mode. figures 5-2 to 5-7 show block diagrams of port 0. caution to use p02/so11 note and p04/sck11 note as general-purpose ports, set serial operation mode register 11 (csim11) and serial clock selection regi ster 11 (csic11) to the default status (00h). note available only in the pd78f0534, 78f0535, 78f05 36, 78f0537, and 78f0537d. figure 5-2. block diagram of p00 internal bus p00/ti000 wr pu rd pu0 pm0 wr port wr pm pu00 alternate function output latch (p00) pm00 ev dd p-ch p0 selector p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 103 figure 5-3. block diagram of p01 p01/ti010/to00 wr pu rd wr port wr pm pu01 pm01 ev dd p-ch pu0 pm0 p0 internal bus alternate function output latch (p01) selector alternate function p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 104 figure 5-4. block diagram of p02 p02/so11 note wr pu rd wr port wr pm pu02 pm02 ev dd p-ch pu0 pm0 p0 internal bus alternate function note output latch (p02) selector p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal note available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d.
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 105 figure 5-5. block diagram of p03 and p05 (a) pd78f0531, 78f0532, 78f0533 p03, p05 wr pu rd wr port wr pm pu03, pu05 pm03, pm05 ev dd p-ch pu0 pm0 p0 internal bus output latch (p03, p05) selector (b) pd78f0534, 78f0535, 78f 0536, 78f0537, 78f0537d p03/si11, p05/ssi11/ti001 wr pu rd wr port wr pm pu03, pu05 pm03, pm05 ev dd p-ch pu0 pm0 p0 internal bus alternate function output latch (p03, p05) selector p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 106 figure 5-6. block diagram of p04 (a) pd78f0531, 78f0532, 78f0533 p04 wr pu rd wr port wr pm pu04 pm04 ev dd p-ch pu0 pm0 p0 internal bus output latch (p04) selector (b) pd78f0534, 78f0535, 78f 0536, 78f0537, 78f0537d p04/sck11 wr pu rd wr port wr pm pu04 pm04 ev dd p-ch pu0 pm0 p0 internal bus alternate function output latch (p04) selector alternate function p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 107 figure 5-7. block diagram of p06 (a) pd78f0531, 78f0532, 78f0533 p06 wr pu rd wr port wr pm pu06 pm06 ev dd p-ch pu0 pm0 p0 internal bus output latch (p06) selector (b) pd78f0534, 78f0535, 78f 0536, 78f0537, 78f0537d p06/ti011/to01 wr pu rd wr port wr pm pu06 pm06 ev dd p-ch pu0 pm0 p0 internal bus alternate function output latch (p06) selector alternate function p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 108 5.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt requ est input, serial interfac e data i/o, clock i/o, and timer i/o. reset signal generation sets port 1 to input mode. figures 5-8 to 5-12 show block diagrams of port 1. caution to use p10/sck10/txd0 and p12/so10 as general-purpose ports, set serial operation mode register 10 (csim10) and serial clock selection regi ster 10 (csic10) to the default status (00h). figure 5-8. block diagram of p10 p10/sck10/txd0 wr pu rd wr port wr pm pu10 alternate function output latch (p10) pm10 alternate function ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 109 figure 5-9. block diagram of p11 and p14 p11/si10/rxd0, p14/rxd6 wr pu rd wr port wr pm pu11, pu14 alternate function output latch (p11, p14) pm11, pm14 ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 110 figure 5-10. block diagram of p12 and p15 p12/so10 p15/toh0 wr pu rd wr port wr pm pu12, pu15 output latch (p12, p15) pm12, pm15 alternate function ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 111 figure 5-11. blo ck diagram of p13 p13/txd6 wr pu rd wr port wr pm pu13 output latch (p13) pm13 alternate function ev dd p-ch internal bus selector pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 112 figure 5-12. block diagram of p16 and p17 p16/toh1/intp5, p17/ti50/to50 wr pu rd wr port wr pm pu16, pu17 alternate function output latch (p16, p17) pm16, pm17 alternate function ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 113 5.2.3 port 2 port 2 is an 8-bit i/o port with an output latch. port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (pm2). this port can also be used for a/d converter analog input. to use p20/ani0 to p27/ani7 as di gital input pins, set them in the di gital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm2. use t hese pins starting from the lower bit. to use p20/ani0 to p27/ani7 as digi tal output pins, set them in the di gital i/o mode by using adpc and in the output mode by using pm2. table 5-4. setting functions of p20/ani0 to p27/ani7 pins adpc pm2 ads p20/ani0 to p27/ani7 pin selects ani. setting prohibited input mode does not select ani. digital input selects ani. setting prohibited digital i/o selection output mode does not select ani. digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited all p20/ani0 to p27/ani7 are set in the anal og input mode when the reset signal is generated. figure 5-13 shows a block diagram of port 2. figure 5-13. block di agram of p20 to p27 internal bus p20/ani0 to p27/ani7 rd wr port wr pm output latch (p20 to p27) pm20 to pm27 selector pm2 a/d converter p2 p2: port register 2 pm2: port mode register 2 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 114 5.2.4 port 3 port 3 is a 4-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when the p30 to p33 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (pu3). this port can also be used for external interrupt request input and timer i/o. reset signal generation sets port 3 to input mode. figures 5-14 and 5-15 show block diagrams of port 3. caution in the pd78f0537d, be sure to pu ll the p31 pin down before a reset release to prevent malfunction. remark the p31 and p32 pins of the pd78f0537d can be used as on-chip debug mode setting pins (ocd1a, ocd1b) when the on-chip debug func tion is used. for details, see chapter 27 on-chip debug function ( pd78f0537d only). figure 5-14. block di agram of p30 to p32 p30/intp1, p31/intp2/ocd1a note , p32/intp3/ocd1b note wr pu rd wr port wr pm pu30 to pu32 alternate function output latch (p30 to p32) pm30 to pm32 ev dd p-ch selector internal bus pu3 pm3 p3 p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal note pd78f0537d only
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 115 figure 5-15. blo ck diagram of p33 p33/intp4/ti51/to51 wr pu rd wr port wr pm pu33 alternate function output latch (p33) pm33 alternate function ev dd p-ch selector internal bus pu3 pm3 p3 p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 116 5.2.5 port 4 port 4 is a 4-bit i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). when the p40 to p43 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (pu4). reset signal generation sets port 4 to input mode. figure 5-16 shows a block diagram of port 4. figure 5-16. block diag ram of p40 to p43 rd p40 to p43 p-ch wr pu wr port wr pm pu40 to pu43 pm40 to pm43 ev dd pu4 pm4 p4 internal bus output latch (p40 to p43) selector p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 117 5.2.6 port 5 port 5 is a 4-bit i/o port with an output latch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). when the p50 to p53 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (pu5). reset signal generation sets port 5 to input mode. figure 5-17 shows a block diagram of port 5. figure 5-17. block diag ram of p50 to p53 rd p50 to p53 p-ch wr pu wr port wr pm pu50 to pu53 pm50 to pm53 ev dd pu5 pm5 p5 internal bus output latch (p50 to p53) selector p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 118 5.2.7 port 6 port 6 is a 4-bit i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). the output of the p60 to p63 pins is n- ch open-drain output (6 v tolerance). this port can also be used for serial interf ace data i/o, clock i/o, and external clock input. reset signal generation sets port 6 to input mode. figures 5-18 to 5-20 show block diagrams of port 6. remark when using p62/exscl0 as an external clock input pin of the serial interface, input a clock of 6.4 mhz to it. figure 5-18. block diagram of p60 and p61 p60/scl0, p61/sda0 rd wr port wr pm alternate function output latch (p60, p61) pm60, pm61 alternate function internal bus selector pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 119 figure 5-19. block diagram of p62 p62/exscl0 rd wr port wr pm alternate function output latch (p62) pm62 internal bus selector pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal figure 5-20. block diagram of p63 p63 rd wr port wr pm output latch (p63) pm63 internal bus selector pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 120 5.2.8 port 7 port 7 is an 8-bit i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p77 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (pu7). this port can also be used for key return input. reset signal generation sets port 7 to input mode. figure 5-21 shows a block diagram of port 7. figure 5-21. block di agram of p70 to p77 p70/kr0 to p77/kr7 wr pu rd wr port wr pm pu70 to pu77 alternate function output latch (p70 to p77) pm70 to pm77 ev dd p-ch selector internal bus pu7 pm7 p7 p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 121 5.2.9 port 12 port 12 is a 5-bit i/o port with an output latch. port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an input por t only for p120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). this port can also be used as pins for external interru pt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecti ng resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. reset signal generation sets port 12 to input mode. figures 5-22 and 5-23 show block diagrams of port 12. caution when using the p121 to p124 pins to connect a resonator fo r the main system clock (x1, x2) or subsystem clock (xt1, xt2), or to input an exter nal clock for the main system clock (exclk) or subsystem clock (exclks), the x1 oscillation mode, xt1 oscillation m ode, or external clock input mode must be set by using the clock operati on mode select register (oscctl) (for details, see 6.3 (1) clock operation mode select register (oscctl) and (3) setti ng of operation mode for subsystem clock pin). the reset value of oscctl is 00h (all of the p121 to p124 pins are i/o port pins). at this time, setting of the pm121 to pm124 and p121 to p124 pins is not necessary. remark the x1 and x2 pins of the pd78f0537d can be used as on-chip debug mode setting pins (ocd0a, ocd0b) when the on-chip debug func tion is used. for details, see chapter 27 on-chip debug function ( pd78f0537d only). figure 5-22. blo ck diagram of p120 p120/intp0/exlvi wr pu rd wr port wr pm pu120 alternate function output latch (p120) pm120 ev dd p-ch pu12 pm12 p12 selector internal bus p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 122 figure 5-23. block di agram of p121 to p124 p122/x2/exclk/ocd0b note , p124/xt2/exclks rd wr port wr pm output latch (p122/p124) pm122/pm124 pm12 p12 rd wr port wr pm output latch (p121/p123) pm121/pm123 pm12 p12 exclk, oscsel/ exclks, oscsels oscctl oscsel/ oscsels oscctl p121/x1/ocd0a note , p123/xt1 oscsel/ oscsels oscctl oscsel/ oscsels oscctl internal bus selector selector p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 oscctl: clock operation mode select register rd: read signal wr : write signal note pd78f0537d only
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 123 5.2.10 port 13 port 13 is a 1-bit output-only port. figure 5-24 shows a block diagram of port 13. figure 5-24. blo ck diagram of p130 rd output latch (p130) wr port p130 internal bus p13 p13: port register 13 rd: read signal wr : write signal remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. p130 set by software reset signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 124 5.2.11 port 14 port 14 is a 6-bit i/o port with an output latch. port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (pm14). when the p140 and p141 pins are used as an input port, use of an on-chip pull- up resistor can be specified in 1-bit units by pull-up resistor option register 14 (pu14). this port can also be used for exter nal interrupt request input, buzzer outpu t, clock output, serial interface data i/o, clock i/o, busy input, and strobe output. reset signal generation sets port 14 to input mode. figures 5-25 shows a block diagram of port 14. figure 5-25. block di agram of p140 and p141 p140/pcl/intp6, p141/buz/intp7 wr pu rd wr port wr pm pu140, pu141 alternate function output latch (p140, p141) pm140, pm141 alternate function ev dd p-ch selector internal bus pu14 pm14 p14 p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 125 5.3 registers controlling port function port functions are controlled by the following four types of registers. ? port mode registers (pm0 to pm7, pm12, pm14) ? port registers (p0 to p7, p12 to p14) ? pull-up resistor option registers (pu0 , pu1, pu3 to pu5, pu7, pu12, pu14) ? a/d port configuration register (adpc) (1) port mode registers (pm0 to pm7, pm12, and pm14) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. when port pins are used as alternate-function pi ns, set the port mode register by referencing 5.5 settings of port mode register and output latch when using alternate function .
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 126 figure 5-26. format of port mode register 7 1 symbol pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w pm17 pm1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w pm27 pm2 pm26 pm25 pm24 pm23 pm22 pm21 pm20 ff22h ffh r/w 1 pm3 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm4 pm43 pm42 pm41 pm40 ff24h ffh r/w pm5 pm53 pm52 pm51 pm50 ff25h ffh r/w pm6 pm63 pm62 pm61 pm60 ff26h ffh r/w pm77 pm7 pm76 pm75 pm74 pm73 pm72 pm71 pm70 ff27h ffh r/w 1 pm12 1 1 pm124 pm123 pm122 pm121 pm120 ff2ch ffh r/w 1 pm14 1 pm141 pm140 ff2eh ffh r/w 1111 1111 1111 1111 pmmn pmn pin i/o mode selection (m = 0 to 7, 12, 14; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 127 (2) port registers (p0 to p7, p12 to p14) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the value of the output latch is read. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 5-27. format of port register 7 0 symbol p0 6 p06 5 p05 4 p04 3 p03 2 p02 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w p17 p1 p16 p15 p14 p13 p12 p11 p10 ff01h 00h (output latch) r/w r/w p27 p2 p26 p25 p24 p23 p22 p21 p20 ff02h 00h (output latch) 0 p3 0 0 0 p33 p32 p31 p30 ff03h 00h (output latch) r/w p4 p43 p42 p41 p40 ff04h 00h (output latch) r/w p5 p53 p52 p51 p50 ff05h 00h (output latch) r/w p6 p63 p62 p61 p60 ff06h 00h (output latch) r/w p77 p7 p76 p75 p74 p73 p72 p71 p70 ff07h 00h (output latch) r/w 0 p12 0 0 p124 p123 p122 p121 p120 ff0ch 00h (output latch) r/w 0 p13 0 0 0 0 0 0 p130 ff0dh 00h (output latch) r/w 0 p14 0 p141 p140 ff0eh 00h (output latch) r/w 0000 0000 0000 0000 m = 0 to 7, 12 to 14; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 128 (3) pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12, and pu14) these registers specify whether the on-ch ip pull-up resistors of p00 to p06, p 10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, or p140 and p141 are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to wh ich the use of an on-chip pull-up resistor has been specified in pu0, pu1, pu3 to pu5, pu7, pu12, and pu14. on-chip pu ll-up resistors cannot be connected to bits set to output mode and bits used as alternate-functi on output pins, regardless of the settings of pu0, pu1, pu3 to pu5, pu7, pu12, and pu14. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 5-28. format of pull-up resistor option register 7 0 symbol pu0 6 pu06 5 pu05 4 pu04 3 pu03 2 pu02 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w pu17 pu1 pu16 pu15 pu14 pu13 pu12 pu11 pu10 ff31h 00h r/w 0 pu3 0 0 0 pu33 pu32 pu31 pu30 ff33h 00h r/w pu4 pu43 pu42 pu41 pu40 ff34h 00h r/w pu5 pu53 pu52 pu51 pu50 ff35h 00h r/w pu77 pu7 pu76 pu75 pu74 pu73 pu72 pu71 pu70 ff37h 00h r/w 0 pu12 0 0 0 0 0 0 pu120 ff3ch 00h r/w 0 pu14 0 pu141 pu140 ff3eh 00h r/w 0000 0000 0000 pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 129 (4) a/d port configuration register (adpc) this register switches the p20/ani0 to p27/ani7 pins to digital i/o of port or anal og input of a/d converter. adpc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 5-29. format of a/d port configuration register (adpc) adpc0 adpc1 adpc2 adpc3 0 0 0 0 digital i/o (d)/analog input (a) switching setting prohibited adpc3 0 1 2 3 4 5 6 7 adpc address: ff2fh after reset: 00h r/w symbol p27/ ani7 a a a a a a a a d p26/ ani6 a a a a a a a d d p25/ ani5 a a a a a a d d d p24/ ani4 a a a a a d d d d p23/ ani3 a a a a d d d d d p22/ ani2 a a a d d d d d d p21/ ani1 a a d d d d d d d p20/ ani0 a d d d d d d d d 0 0 0 0 0 0 0 0 1 adpc2 0 0 0 0 1 1 1 1 0 adpc1 0 0 1 1 0 0 1 1 0 adpc0 0 1 0 1 0 1 0 1 0 other than above cautions 1. set the channel used for a/d conversion to the input mode by using port mode register 2 (pm2). 2. do not set a pin to be used as a digital i/o pin with adpc by using the analog input channel specification register (ads). 3. if data is written to adpc, a wait cycle is ge nerated. do not write data to adpc when the cpu is operating on the subsystem clock and the pe ripheral hardware clock is stopped. for details, see chapter 31 cautions for wait.
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 130 5.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. caution in the case of 1-bit memory manipulation instru ction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 5.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruct ion, and the output latch content s are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. 5.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 5.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode the pin level is read and an operation is performed on its cont ents. the result of the op eration is written to the output latch, but since the output buffer is off, the pin status does not change. the data of the output latch is clear ed when a reset signal is generated.
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 131 5.5 settings of port mode register and output latch when using alternate function to use the alternate function of a por t pin, set the port mode register and output latch as shown in table 5-5. table 5-5. settings of port mode register a nd output latch when using alternate function (1/2) alternate function pin name function name i/o pm p p00 ti000 input 1 ti010 input 1 p01 to00 output 0 0 p02 so11 note output 0 0 p03 si11 note input 1 input 1 p04 sck11 note output 0 1 ssi11 note input 1 p05 ti001 note input 1 ti011 note input 1 p06 to01 note output 0 0 input 1 sck10 output 0 1 p10 txd0 output 0 1 si10 input 1 p11 rxd0 input 1 p12 so10 output 0 0 p13 txd6 output 0 1 p14 rxd6 input 1 p15 toh0 output 0 0 toh1 output 0 0 p16 intp5 input 1 ti50 input 1 p17 to50 output 0 0 note available only in the pd78f0534, 78f0535, 78f05 36, 78f0537, and 78f0537d. remark : don?t care pm : port mode register p : port output latch
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 132 table 5-5. settings of port mode register a nd output latch when using alternate function (2/2) alternate function pin name function name i/o pm p p20 to p27 note 1 ani0 to ani7 note 1 input 1 p30 to p32 intp1 to intp3 input 1 intp4 input 1 ti51 input 1 p33 to51 output 0 0 p60 scl0 i/o 0 0 p61 sda0 i/o 0 0 p62 exscl0 input 1 p70 to p77 kr0 to kr7 input 1 intp0 input 1 p120 exlvi input 1 p121 x1 note 2 ? x2 note 2 ? p122 exclk note 2 input p123 xt1 note 2 ? xt2 note 2 ? p124 exclks note 2 input pcl output 0 0 p140 intp6 input 1 buz output 0 0 p141 intp7 input 1 remarks 1. : don?t care pm : port mode register p : port output latch 2. the x1, x2, p31, and p32 pins of the pd78f0537d can be used as on-chip debug mode setting pins (ocd0a, ocd0b, ocd1a, ocd1b) when the on -chip debug function is used. for details, see chapter 27 on-chip debug function ( pd78f0537d only). (notes 1 and 2 are listed on the next page.)
chapter 5 port functions preliminary user?s manual u17260ej3v1ud 133 notes 1. the function of the ani0/p20 to ani7/p27 pins ca n be selected by using t he a/d port configuration register (adpc), the analog input channel specification register (ads), and pm2. table 5-6. setting functions of ani0/p20 to ani7/p27 pins adpc pm2 ads ani0/p20 to ani7/p27 pins selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited selects ani. setting prohibited input mode does not select ani. digital input selects ani. setting prohibited digital i/o selection output mode does not select ani. digital output 2. when using the p121 to p124 pins to connect a resonator for the main system clock (x1, x2) or subsystem clock (xt1, xt2), or to input an exte rnal clock for the main system clock (exclk) or subsystem clock (exclks), the x1 oscillation mode , xt1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (oscctl) (for details, see 6.3 (1) clock operation mode select register (oscctl) and (3) setting of operation mode for subsystem clock pin ). the reset value of os cctl is 00h (all of the p121 to p124 are i/o port pins). at this time, setting of pm121 to pm124 and p121 to p124 is not necessary.
preliminary user?s manual u17260ej3v1ud 134 chapter 6 clock generator 6.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three kinds of system clo cks and clock oscillators are selectable. (1) main system clock <1> x1 oscillator this circuit oscillates a clock of f x = 1 to 20 mhz by connecting a resonator to x1 and x2. oscillation can be stopped by executing the stop inst ruction or using the main osc control register (moc). <2> internal high-speed oscillator this circuit oscillates a clock of f rh = 8 mhz (typ.). after a reset release, the cpu always starts operating with this internal high-speed oscillation clock. oscillation can be stopped by executing the stop instruction or using the internal oscillation mode register (rcm). an external main system clock (f exclk = 1 to 20 mhz) can also be supplied from the exclk/x2/p122 pin. an external main system clock input can be disabled by executing the stop in struction or using rcm. as the main system clock, a high-spee d system clock (x1 clock or external ma in system clock) or internal high- speed oscillation clock can be selected by using the main clock mode register (mcm). (2) subsystem clock ? subsystem clock oscillator this circuit oscillates at a frequency of f xt = 32.768 khz by connecting a 32.768 khz resonator across xt1 and xt2. oscillation can be stopped by using the pr ocessor clock control register (pcc) and clock operation mode select register (oscctl). an external subsystem clock (f exclks = 32.768 khz) can also be supplied from the exclks/xt2/p124 pin. an external subsystem clock input can be disabled by setting pcc and oscctl. remarks 1. f x : x1 clock oscillation frequency 2. f rh : internal high-speed oscillation clock frequency 3. f exclk : external main system clock frequency 4. f xt : xt1 clock oscillation frequency 5. f exclks : external subsystem clock frequency
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 135 (3) internal low-speed oscillation clock (clock for watchdog timer) ? internal low-speed oscillator this circuit oscillates a clock of f rl = 240 khz (typ.). after a reset releas e, the internal low-speed oscillation clock always starts operating. oscillation can be stopped by using the internal oscill ation mode register (rcm) when ?internal low-speed oscillator can be stopped by software? is set by option byte. the internal low-speed oscillation clock cannot be us ed as the cpu clock. the following hardware operates with the internal low-speed oscillation clock. ? watchdog timer ? tmh1 (when f rl , f rl /2 7 , or f rl /2 9 is selected) remark f rl : internal low-speed oscillation clock frequency 6.2 configuration of clock generator the clock generator includes the following hardware. table 6-1. configuration of clock generator item configuration control registers clock operation mode select register (oscctl) processor clock control register (pcc) internal oscillation mode register (rcm) main osc control register (moc) main clock mode register (mcm) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) oscillators x1 oscillator xt1 oscillator internal high-speed oscillator internal low-speed oscillator
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 136 figure 6-1. block diag ram of clock generator option byte 1: cannot be stopped 0: can be stopped internal oscillation mode register (rcm) lsrstop rsts rstop internal high- speed oscillator (8 mhz (typ.)) internal low- speed oscillator (240 khz (typ.)) f rl clock operation mode select register (oscctl) oscsels exclks xt1/p123 xt2/exclks/ p124 f sub peripheral hardware clock (f prs ) watchdog timer, 8-bit timer h1 watch timer, clock output 1/2 cpu clock (f cpu ) processor clock control register (pcc) css pcc2 cls pcc1 pcc0 prescaler main system clock switch f xp peripheral hardware clock switch x1 oscillation stabilization time counter osts1 osts0 osts2 oscillation stabilization time select register (osts) 3 most 16 most 15 most 14 most 13 most 11 oscillation stabilization time counter status register (ostc) controller mcm0 xsel mcs mstop stop exclk oscsel amph clock operation mode select register (oscctl) 4 f xp 2 f xp 2 2 f xp 2 3 f xp 2 4 main clock mode register (mcm) main clock mode register (mcm) main osc control register (moc) f rh internal bus internal bus high-speed system clock oscillator crystal/ceramic oscillation external input clock x1/p121 x2/exclk/ p122 f xh f sub 2 crystal oscillation external input clock subsystem clock oscillator f x f exclk f xt f exclks xtstart to subsystem clock oscillator xtstart processor clock control register (pcc) selector
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 137 remarks 1. f x : x1 clock oscillation frequency 2. f rh : internal high-speed oscillation clock frequency 3. f exclk : external main system clock frequency 4. f xh : high-speed system clock oscillation frequency 5. f xp : main system clock oscillation frequency 6. f prs : peripheral hardware clock oscillation frequency 7. f cpu : cpu clock oscillation frequency 8. f xt : xt1 clock oscillation frequency 9. f exclks : external subsystem clock frequency 10. f sub : subsystem clock oscillation frequency 11. f rl : internal low-speed oscillation clock frequency 6.3 registers controlling clock generator the following seven registers are used to control the clock generator. ? clock operation mode sele ct register (oscctl) ? processor clock control register (pcc) ? internal oscillation mode register (rcm) ? main osc control register (moc) ? main clock mode register (mcm) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) (1) clock operation mode select register (oscctl) this register selects the operation mo des of the high-speed system and s ubsystem clocks, and the gain of the on-chip oscillator. oscctl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 138 figure 6-2. format of clock operati on mode select register (oscctl) address: ff9fh after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 <0> oscctl exclk oscsel exclks note oscsels note 0 0 0 amph exclk oscsel high-speed system clock pin operation mode p121/x1 pin p122/x2/exclk pin 0 0 i/o port mode i/o port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 i/o port mode i/o port 1 1 external clock input mode i/o port external clock input amph operating frequency control 0 1 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz note exclks and oscsels are used in combinatio n with xtstart (bit 6 of the processor clock control register (pcc)). see (3) setting of operation mode for subsystem clock pin . cautions 1. be sure to set amph to 1 if the high-speed system cl ock oscillation frequency exceeds 10 mhz. 2. set amph before setting the peripheral functions after a reset release. the value of amph can be changed only once after a reset release. the clock supply to the cpu is stopped for 5 s (min.) after amph has been set to 1. 3. if the stop instruction is executed with amph set to 1 when the internal high- speed oscillation clock or ex ternal main system clock is used as the cpu clock, then the clock supply to the cpu is stopped for 5 s (min.) after the stop mode has been released. if th e x1 clock is used as th e cpu clock, oscillation stabilization time is counted after the stop mode has been released. 4. to change the value of exclk and oscsel, be sure to confirm that bit 7 (mstop) of the main osc control register (moc) is 1 (the x1 oscillator stops or the external clock from the exclk pin is disabled). remark f xh : high-speed system clock oscillation frequency
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 139 (2) processor clock control register (pcc) this register is used to select t he cpu clock, the division ratio, and operation mode for subsystem clock. pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pcc to 01h. figure 6-3. format of processor clock control register (pcc) address: fffbh after reset: 01h r/w note 1 symbol 7 6 <5> <4> 3 2 1 0 pcc 0 xtstart note2 cls css 0 pcc2 pcc1 pcc0 cls cpu clock status 0 main system clock 1 subsystem clock notes 1. bit 5 is read-only. 2. xtstart is used in combination with exc lks and oscsels (bits 5 and 4 of the clock operation mode select register (oscctl)). see (3) setting of operation mode for subsystem clock pin . caution be sure to clear bits 3 and 7 to 0. remarks 1. f xp : main system clock oscillation frequency 2. f sub : subsystem clock oscillation frequency the fastest instruction can be executed in 2 clocks of t he cpu clock in the 78k0/ke2. therefore, the relationship between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 6-2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 0 1 0 0 f xp /2 4 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 f sub /2 other than above setting prohibited
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 140 table 6-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu main system clock high-speed system clock note internal high-speed oscillation clock note subsystem clock cpu clock (f cpu ) at 10 mhz operation at 20 mhz operation at 8 mhz (typ.) operation at 32.768 khz operation f xp 0.2 s 0.1 s 0.25 s (typ.) ? f xp /2 0.4 s 0.2 s 0.5 s (typ.) ? f xp /2 2 0.8 s 0.4 s 1.0 s (typ.) ? f xp /2 3 1.6 s 0.8 s 2.0 s (typ.) ? f xp /2 4 3.2 s 1.6 s 4.0 s (typ.) ? f sub /2 ? ? 122.1 s note the main clock mode register (mcm) is used to set the main system clock supplied to cpu clock (high- speed system clock/internal high- speed oscillation clock) (see figure 6-6 ). (3) setting of operation mode for subsystem clock pin the operation mode for the subsystem clock pin can be se t by using bit 6 (xtstart) of the processor clock control register (pcc) and bits 5 and 4 (exclks, osc sels) of the clock operation mode select register (oscctl) in combination. table 6-3. setting of operati on mode for subsystem clock pin pcc oscctl bit 6 bit 5 bit 4 xtstart exclks oscsels subsystem clock pin operation mode p123/xt1 pin p124/xt2/exclks pin 0 0 0 i/o port mode i/o port 0 0 1 xt1 oscillation mode crystal resonator connection 0 1 0 i/o port mode i/o port 0 1 1 external clock input mode i/o port external clock input 1 xt1 oscillation mode crystal resonator connection caution confirm that bit 5 (cls) of the processor clock cont rol register (pcc) is 0 (cpu is operating with main system clock) when changing the current valu es of xtstart, exclks, and oscsels. remark : don?t care
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 141 (4) internal oscillati on mode register (rcm) this register sets the operation mode of internal oscillator. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h note 1 . figure 6-4. format of internal oscillation mode register (rcm) address: ffa0h after reset: 80h note 1 r/w note 2 symbol <7> 6 5 4 3 2 <1> <0> rcm rsts 0 0 0 0 0 lsrstop rstop rsts status of internal high-speed oscillator 0 waiting for accuracy stabilizati on of internal high-speed oscillator 1 stability operating of internal high-speed oscillator lsrstop internal low-speed oscillator oscillating/stopped 0 internal low-speed oscillator oscillating 1 internal low-s peed oscillator stopped rstop internal high-speed oscillator oscillating/stopped 0 internal high-spe ed oscillator oscillating 1 internal high-speed oscillator stopped notes 1. the value of this register is 00h immedi ately after a reset release but automatically changes to 80h after internal high-speed oscillator has been stabilized. 2. bit 7 is read-only. caution when setting rstop to 1, be sure to confirm that the cpu operates with a clock other than the internal high -speed oscillation clock. sp ecifically, set under either of the following conditions. ? when mcs = 1 (when cpu operates with the high-speed system clock) ? when cls = 1 (when cpu opera tes with the subsystem clock) in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting rstop to 1.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 142 (5) main osc control register (moc) this register selects the operati on mode of the high-speed system clock. this register is used to stop the x1 oscillator or to disable an external clock input from the exclk pin when the cpu operates with a clock other than the high-speed system clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h. figure 6-5. format of main osc control register (moc) address: ffa2h after reset: 80h r/w symbol <7> 6 5 4 3 2 1 0 moc mstop 0 0 0 0 0 0 0 control of high-speed system clock operation mstop x1 oscillation mode external clock input mode 0 x1 oscillator operating external clock from exclk pin is enabled 1 x1 oscillator stopped external clock from exclk pin is disabled cautions 1. when setting ms top to 1, be sure to confirm that the cpu operates with a clock other than the high-speed system clock. specifically , set under either of the following conditions. ? when mcs = 0 (when cpu operates with the internal high-speed oscillation clock) ? when cls = 1 (when cpu opera tes with the subsystem clock) in addition, stop peripheral hardware th at is operating on the high-speed system clock before setting mstop to 1. 2. do not clear mstop to 0 while bit 6 (oscsel) of the clock operation mode select register (oscctl) is 0 (i/o port mode). 3. the peripheral hardware cannot operate when the pe ripheral hardware clock is stopped. to resume the operation of the peripheral ha rdware after the peripheral hardware clock has been stoppe d, initialize the peripheral hardware.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 143 (6) main clock mode register (mcm) this register selects the main system clock supplied to cpu clock and clock supplied to peripheral hardware clock. mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 6-6. format of main clock mode register (mcm) address: ffa1h after reset: 00h r/w note symbol 7 6 5 4 3 <2> <1> <0> mcm 0 0 0 0 0 xsel mcs mcm0 selection of clock supplied to main system clock and peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) mcs main system clock status 0 operates with internal high-speed oscillation clock 1 operates with hi gh-speed system clock note bit 1 is read-only. cautions 1. xsel can be change d only once after a reset release. 2. a clock other than f prs is supplied to the following peripheral functions regardless of the se tting of xsel and mcm0. ? watchdog timer (operates with intern al low-speed oscillation clock) ? when ?f rl ?, ?f rl /2 7 ?, or ?f rl /2 9 ? is selected as the count clock for 8-bit timer h1 (operates with internal low-speed oscillation clock) ? peripheral hardware selects the ext ernal clock as the clock source (except when the external count clock of tm 0n (n = 0, 1) is selected (ti00n pin valid edge))
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 144 (7) oscillation stabilization time c ounter status register (ostc) this is the register that indicates t he count status of the x1 clock oscillati on stabilization time counter. when x1 clock oscillation starts with the intern al high-speed oscillation clock or su bsystem clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lv i, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 6-7. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status f x = 10 mhz f x = 20 mhz 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 0 0 2 14 /f x min. 1.64 ms min. 819.2 s min. 1 1 1 1 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 2 16 /f x min. 6.55 ms min. 3.27 ms min. cautions 1. after the above time has elapsed, th e bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 145 (8) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elapsed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 6-8. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 10 mhz f x = 20 mhz 0 0 1 2 11 /f x 204.8 s 102.4 s 0 1 0 2 13 /f x 819.2 s 409.6 s 0 1 1 2 14 /f x 1.64 ms 819.2 s 1 0 0 2 15 /f x 3.27 ms 1.64 ms 1 0 1 2 16 /f x 6.55 ms 3.27 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 4. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 146 6.4 system clock oscillator 6.4.1 x1 oscillator the x1 oscillator oscillates with a cryst al resonator or ceramic resonator (1 to 20 mhz) connected to the x1 and x2 pins. figure 6-9 shows an example of the exte rnal circuit of the x1 oscillator. figure 6-9. example of external circuit of x1 oscillator (crystal or ceramic oscillation) v ss x1 x2 crystal resonator or ceramic resonator cautions are listed on the next page. 6.4.2 xt1 oscillator the xt1 oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. figure 6-10 shows an example of the exte rnal circuit of the xt1 oscillator. figure 6-10. example of external circuit of xt1 oscillator (crystal oscillation) xt2 v ss xt1 32.768 khz cautions are listed on the next page.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 147 cautions 1. when using the x1 oscillator and xt1 o scillator, wire as follows in the area enclosed by the broken lines in the figures 6-9 and 6-10 to avoid an adverse e ffect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal li nes. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the os cillator capacitor the same potential as v ss . do not ground the capacitor to a ground patter n through which a high current flows. do not fetch signals from the oscillator. note that the xt1 oscillator is designed as a low-amplitude circuit for reducing power consumption. figure 6-11 shows examples of incorrect resonator connection. figure 6-11. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 148 figure 6-11. examples of incorr ect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. when x2 and xt1 are wired in paralle l, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 149 6.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock for low power consumption operat ions, or if not using the subsystem clock as an i/o port, set the xt1 and xt2 pins to i/o mode (oscsels = 0) and connect them as follows. input (pm123/pm124 = 1): i ndependently connect to v dd or v ss via a resistor. output (pm123/pm124 = 0): leave open. remark oscsels: bit 4 of clock operati on mode select register (oscctl) pm123, pm124: bits 3 and 4 of port mode register 12 (pm12) 6.4.4 internal hi gh-speed oscillator the internal high-speed oscillator is incorporated in the 78k0/ke2. oscillation can be controlled by the internal oscillation mode register (rcm). after a reset release, the internal high-speed oscilla tor automatically starts oscillation (8 mhz (typ.)). 6.4.5 internal low-speed oscillator the internal low-speed oscillator is incorporated in the 78k0/ke2. the internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer h1. the internal low-speed oscillation clock cannot be used as the cpu clock. ?can be stopped by software? or ?cannot be stopped? ca n be selected by the option byte. when ?can be stopped by software? is set, oscillation can be controlled by the internal oscillation mode register (rcm). after a reset release, the internal low-speed oscillator automatically starts oscillati on, and the watchdog timer is driven (240 khz (typ.)) if the watchdog timer operation is enabled using the option byte. 6.4.6 prescaler the prescaler generates various clocks by dividing the main system clock when the ma in system clock is selected as the clock to be supplied to the cpu.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 150 6.5 clock generator operation the clock generator generates the following clocks and contro ls the operation modes of the cpu, such as standby mode (see figure 6-1 ). ? main system clock f xp ? high-speed system clock f xh x1 clock f x external main system clock f exclk ? internal high-speed oscillation clock f rh ? subsystem clock f sub ? xt1 clock f xt ? external subsystem clock f exclks ? internal low-speed oscillation clock f rl ? cpu clock f cpu ? peripheral hardware clock f prs the cpu starts operation when the internal high-speed osc illator starts outputting after a reset release in the 78k0/ke2, thus enabling the following. (1) enhancement of security function when the x1 clock is set as the cpu clock by the defaul t setting, the device cannot operate if the x1 clock is damaged or badly connected and therefore does not operate after reset is released. however, the start clock of the cpu is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release. consequently , the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) improvement of performance because the cpu can be started with out waiting for the x1 clock oscillation stabilization time, the total performance can be improved. when the power supply voltage is turned on, the clock generator operation is shown in figure 6-12.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 151 figure 6-12. clock generator operation wh en power supply voltage is turned on (when 1.59 v poc mode is set (option byte: pocmode = 0)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note starting x1 oscillation is specified by software. starting xt1 oscillation is specified by software. reset processing (20 s (typ.)) <3> waiting for voltage stabilization internal reset signal 0 v 1.59 v (typ.) 1.8 v 0.5 v/ms (max.) power supply voltage (v dd ) <1> <2> <4> <5> <5> <4> waiting for oscillation accuracy stabilization (3.24 ms (typ.)) <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 1.59 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> when the power supply voltage rises with a slope of 0.5 v/ms (max.), the cpu starts operation on the internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage of the power supply and regulator have elapsed, and then reset processing is performed. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 6.6.1 example of controlling high- speed system clock and (1) in 6.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 6.6.1 example of controlli ng high-speed system clock and (3) in 6.6.3 example of controlling subsystem clock ). note when releasing a reset (above figure) or releasing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the oscillation stab ilization time for the x1 clock using the oscillation stabilization time counter status r egister (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation stabilization time when releasing stop mode using the oscillation stabilization time select register (osts). cautions 1. if the voltage rises with a slope of less than 0.5 v/ms (ma x.) from power application until the voltage reaches 1.8 v, input a lo w level to the reset pin from power application until the voltage reaches 1.8 v, or set the 2.7 v/1.59 v poc mode by using the option byte (pocmode = 1) (see figure 6-13). by doing so, the cpu operates with the same timing as <2> and thereafter in figure 6-12 after re set release by the reset pin. 2. it is not necessary to wait for the oscillation stabilization ti me when an external clock input from the exclk and exc lks pins is used.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 152 remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed o scillation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 6.6.1 example of co ntrolling high-speed system clock , (3) in 6.6.2 example of controlling inte rnal high-speed oscillation clock , and (4) in 6.6.3 example of controlling subsystem clock ). figure 6-13. clock generator operation wh en power supply voltage is turned on (when 2.7 v/1.59 v poc mode is set (option byte: pocmode = 1)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note starting x1 oscillation is specified by software. starting xt1 oscillation is specified by software. waiting for oscillation accuracy stabilization internal reset signal 0 v 2.7 v (typ.) power supply voltage (v dd ) <1> <3> <2> <4> <5> reset processing (20 s (typ.)) <4> <5> <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 2.7 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> after the reset is released and reset processing is performed, the cpu starts operation on the internal high- speed oscillation clock. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 6.6.1 example of controlling high- speed system clock and (1) in 6.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 6.6.1 example of controlli ng high-speed system clock and (3) in 6.6.3 example of controlling subsystem clock ). note when releasing a reset (above figure) or releasing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the oscillation stab ilization time for the x1 clock using the oscillation stabilization time counter status r egister (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation stabilization time when releasing stop mode using the oscillation stabilization time select register (osts). caution it is not necessary to wait for the oscillation stabilization time when an externa l clock input from the exclk and exclks pins is used.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 153 remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed o scillation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 6.6.1 example of co ntrolling high-speed system clock , (3) in 6.6.2 example of controlling inte rnal high-speed oscillation clock , and (4) in 6.6.3 example of controlling subsystem clock ). 6.6 controlling clock 6.6.1 controlling hi gh-speed system clock the following two types of high-s peed system clocks are available. ? x1 clock: crystal/ceramic resonator is connected across the x1 and x2 pins. ? external main system clock: exter nal clock is input to the exclk pin. when the high-speed system clock is not used, the x1/p 121 and x2/exclk/p122 pins can be used as i/o port pins. caution the x1/p121 and x2/exclk/p122 pins are in the i/o port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating x1 clock (2) when using external main system clock (3) when using high-speed system clock as cpu clock and peripheral hardware clock (4) when stopping high-speed system clock (1) example of setting procedure when oscillating the x1 clock <1> setting frequency (oscctl register) using amph, set the gain of the on-chip osci llator according to the frequency to be used. amph note operating frequency control 0 1 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz note set amph before setting the peripheral functions a fter a reset release. the value of amph can be changed only once after a reset release. when amph is set to 1, the clock supply to the cpu is stopped for 5 s (min.). remark f xh : high-speed system clock oscillation frequency <2> setting p121/x1 and p122/x2/exclk pins and selecti ng x1 clock or external clock (oscctl register) when exclk is cleared to 0 and oscsel is set to 1, the mode is switched from port mode to x1 oscillation mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 0 1 x1 oscillation mode crystal/ceramic resonator connection <3> controlling oscillation of x1 clock (moc register) if mstop is cleared to 0, the x1 oscillator starts oscillating.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 154 <4> waiting for the stabilization of the oscillation of x1 clock check the ostc register and wait for the necessary time. during the wait time, other software processing c an be executed with the internal high-speed oscillation clock. cautions 1. do not change the value of exclk and oscsel while the x1 clock is operating. 2. set the x1 clock after th e supply voltage has r eached the operable volt age of the clock to be used (see chapter 29 electr ical specifications (target)). (2) example of setting procedure when using the external main system clock <1> setting frequency (oscctl register) using amph, set the frequency to be used. amph note operating frequency control 0 1 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz note set amph before setting the peripheral functions a fter a reset release. the value of amph can be changed only once after a reset release. when amph is set to 1, the clock supply to the cpu is stopped for 5 s (min.). remark f xh : high-speed system clock oscillation frequency <2> setting p121/x1 and p122/x2/exclk pins and selecting operation mode (oscctl register) when exclk and oscsel are set to 1, the mode is switched from port mode to external clock input mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 1 1 external clock input mode i/o port external clock input <3> controlling external main system clock input (moc register) when mstop is cleared to 0, the input of the external main system clock is enabled. cautions 1. do not change the value of exclk a nd oscsel while the external main system clock is operating. 2. set the external main system clock afte r the supply voltage h as reached the operable voltage of the clock to be used (see chapter 29 electrical specifications (target)). (3) example of setting procedure when using high-speed system clo ck as cpu clock and peripheral hardware clock <1> setting high-speed system clock oscillation note (see 6.6.1 (1) example of setting proce dure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when hi gh-speed system clock is already operating.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 155 <2> setting the high-speed system clock as the main system clock (mcm register) when xsel and mcm0 are set to 1, the high-speed syst em clock is supplied as the main system clock and peripheral hardware clock. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) caution if the high-speed system clock is selected as the main syst em clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> setting the main system clock as the cpu clo ck and selecting the division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 0 other than above setting prohibited (4) example of setting procedure when stopping the high-speed system clock the high-speed system clock can be st opped in the foll owing two ways. ? executing the stop instruction to set the stop mode ? setting mstop to 1 and stopping the x1 oscillation (dis abling clock input if the external clock is used) (a) to execute a stop instruction <1> setting to stop peripheral hardware stop peripheral hardware that c annot be used in the stop mode (f or peripheral hardware that cannot be used in stop mode, see chapter 21 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and x1 oscillation is stopped (the input of the ex ternal clock is disabled).
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 156 (b) to stop x1 oscillation (disabling exter nal clock input) by setting mstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is oper ating on a clock other than the high-speed system clock. when cls = 0 and mcs = 1, the high-speed system cl ock is supplied to the cpu, so change the cpu clock to the subsystem clock or internal high-speed oscillation clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the high-speed system clock (moc register) when mstop is set to 1, x1 oscillation is stopp ed (the input of the external clock is disabled). caution be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. 6.6.2 example of controlling inte rnal high-speed oscillation clock the following describes examples of clock setting procedures for the following cases. (1) when restarting oscillation of the internal high-speed oscillation clock (2) when using internal high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock (3) when stopping the internal high-speed oscillation clock (1) example of setting procedure wh en restarting oscillation of the in ternal high-speed oscillation clock note 1 <1> setting restart of oscillation of the intern al high-speed oscillation clock (rcm register) when rstop is cleared to 0, the internal high-speed oscillation clock starts operating. <2> waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (rcm register) wait until rsts is set to 1 note 2 . notes 1. after a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the cpu clock. 2. this wait time is not necessary if high accura cy is not necessary for the cpu clock and peripheral hardware clock.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 157 (2) example of setting procedure when using intern al high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clo ck as peripheral hardware clock <1> ? restarting oscillation of the internal high-speed oscillation clock note (see 6.6.2 (1) example of setting procedure when restarting internal high-speed oscillation clock ). ? oscillating the high-speed system clock note (this setting is required when using the high-speed system clock as the peripheral hardware clock. see 6.6.1 (1) example of setting proced ure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when the internal high-speed oscillation clock or high- speed system clock is already operating. <2> selecting the clock s upplied as the main system clock and peri pheral hardware clock (mcm register) set the main system clock and peripheral hardware clock using xsel and mcm0. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) <3> selecting the cpu clock division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 0 other than above setting prohibited (3) example of setting procedure when stoppi ng the internal high-speed oscillation clock the internal high-speed oscillation clock can be stopped in the following two ways. ? executing the stop instruction to set the stop mode ? setting rstop to 1 and stopping the internal high-speed oscillation clock (a) to execute a stop instruction <1> setting of peripheral hardware stop peripheral hardware that c annot be used in the stop mode (f or peripheral hardware that cannot be used in stop mode, see chapter 21 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and internal high- speed oscillation clock is stopped.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 158 (b) to stop internal high-speed o scillation clock by setting rstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operat ing on a clock other than the internal high-speed oscillation clock. when cls = 0 and mcs = 0, the internal high-speed oscillation clock is supplied to the cpu, so change the cpu clock to the high-spe ed system clock or subsystem clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the internal high-speed oscillation clock (rcm register) when rstop is set to 1, internal high-speed oscillation clock is stopped. caution be sure to confirm that mcs = 1 or cls = 1 when setting rstop to 1. in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. 6.6.3 example of cont rolling subsystem clock the following two types of sub system clocks are available. ? xt1 clock: crystal/ceramic resonator is connected across the xt1 and xt2 pins. ? external subsystem clock: external clock is input to the exclks pin. when the subsystem clock is not us ed, the xt1/p123 and xt2/ exclks/p124 pins can be used as i/o port pins. caution the xt1/p123 and xt2/exclks/p124 pins are in the i/o port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating xt1 clock (2) when using external subsystem clock (3) when using subsystem clock as cpu clock (4) when stopping subsystem clock (1) example of setting procedur e when oscillating the xt1 clock <1> setting xt1 and xt2 pins and selectin g operation mode (pcc and oscctl registers) when xtstart, exclks, and oscsels are set as any of the following, the mode is switched from port mode to xt1 oscillation mode. xtstart exclks oscsels operation mode of subsystem clock pin p123/xt1 pin p124/xt2/ exclks pin 0 0 1 1 xt1 oscillation mode crystal/ceramic resonator connection remark : don?t care <2> waiting for the stabilization of the subsystem clock oscillation wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. caution do not change the value of xtstart, exclks, and oscsel s while the subsystem clock is operating.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 159 (2) example of setting procedure when using the external subsystem clock <1> setting xt1 and xt2 pins, selecting xt1 clock/ external clock and controlling oscillation (pcc and oscctl registers) when xtstart is cleared to 0 and exclks and oscsel s are set to 1, the mode is switched from port mode to external clock input mode. in this ca se, input the external clock to the exclks/xt2/p124 pins. xtstart exclks oscsels operation mode of subsystem clock pin p123/xt1 pin p124/xt2/ exclks pin 0 1 1 external clock input mode i/o port external clock input caution do not change the value of xtstart, exclks, and oscsel s while the subsystem clock is operating. (3) example of setting procedure when us ing the subsystem cl ock as the cpu clock <1> setting subsystem clock oscillation note (see 6.6.3 (1) example of setting proce dure when oscillating the xt1 clock and (2) example of setting procedure when using the external subsystem clock .) note the setting of <1> is not necessary when while the subsystem clock is operating. <2> switching the cpu clock (pcc register) when css is set to 1, the subsystem clock is supplied to the cpu. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 f sub /2 1 other than above setting prohibited (4) example of setting procedure wh en stopping the subsystem clock <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operat ing on a clock other than the subsystem clock. when cls = 1, the subsystem clock is supplied to t he cpu, so change the cpu clock to the internal high-speed oscillation clock or high-speed system clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the subsystem clock (oscctl register) when oscsels is cleared to 0, xt1 oscillation is stop ped (the input of the external clock is disabled). caution1. be sure to confirm that cls = 0 when clearing oscsels to 0. in addition, stop the watch timer if it is operating on the subsystem clock. 2. the subsystem clock oscillation cannot be stopped using the stop instruction.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 160 6.6.4 example of controlling in ternal low-speed oscillation clock the internal low-speed oscillation clock cannot be used as the cpu clock. only the following peripheral hardware can operate with this clock. ? watchdog timer ? 8-bit timer h1 (if f rl is selected as the count clock) in addition, the following operation modes can be selected by the option byte. ? internal low-speed oscillator cannot be stopped ? internal low-speed oscillator can be stopped by software the internal low-speed oscillator autom atically starts oscillation after a reset release, and the watchdog timer is driven (240 khz (typ.)) if the watchdog timer operation has been enabled by the option byte. (1) example of setting procedure when stoppi ng the internal low-speed oscillation clock <1> setting lsrstop to 1 (rcm register) when lsrstop is set to 1, the internal low-speed oscillation clock is stopped. (2) example of setting procedure when restarting osc illation of the internal low-speed oscillation clock <1> clearing lsrstop to 0 (rcm register) when lsrstop is cleared to 0, the internal low-speed oscillation clock is restarted. caution if ?internal low-speed oscillator cannot be st opped? is selected by the option byte, oscillation of the internal low-speed oscillati on clock cannot be controlled. 6.6.5 clocks supplied to cp u and peripheral hardware the following table shows the relation among the clocks supplied to the cpu and peripheral hardware, and setting of registers. table 6-4. clocks supplied to cpu and peripheral hardware, and register setting supplied clock clock supplied to cpu clock su pplied to peripheral hardware xsel css mcm0 exclk internal high-speed oscillation clock 0 0 x1 clock 1 0 0 0 internal high-speed oscillation clock external main system clock 1 0 0 1 x1 clock 1 0 1 0 external main system clock 1 0 1 1 internal high-speed oscillation clock 0 1 1 1 0 0 x1 clock 1 1 1 0 1 1 0 1 subsystem clock external main system clock 1 1 1 1 remarks 1. xsel: bit 2 of the main clock mode register (mcm) 2. css: bit 4 of the processor clock control register (pcc) 3. mcm0: bit 0 of mcm 4. exclk: bit 7 of the clock operat ion mode select register (oscctl) 5. : don?t care
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 161 6.6.6 cpu clock stat us transition diagram figure 6-14 shows the cpu clock status transition diagram of this product. figure 6-14. cpu clock stat us transition diagram (when 1.59 v poc mode is set (option byte: pocmode = 0)) power on reset release v dd 1.59 v (typ.) v dd 1.8 v (min.) v dd < 1.59 v (typ.) internal low-speed oscillation: woken up internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (i/o port mode) xt1 oscillation/exclks input: stops (i/o port mode) internal low-speed oscillation: operating internal high-speed oscillation: operating x1 oscillation/exclk input: stops (i/o port mode) xt1 oscillation/exclks input: stops (i/o port mode) cpu: operating with internal high- speed oscillation internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu xt1 oscillation/exclks input: selectable by cpu cpu: internal high- speed oscillation stop internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation/exclks input: stops cpu: internal high- speed oscillation halt internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: operable xt1 oscillation/exclks input: operable cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input stop cpu: x1 oscillation/exclk input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating xt1 oscillation/exclks input: selectable by cpu internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: stops internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operating xt1 oscillation/exclks input: operable cpu: operating with xt1 oscillation or exclks input cpu: xt1 oscillation/exclks input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: selectable by cpu xt1 oscillation/exclks input: operating internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operable xt1 oscillation/exclks input: operating (b) (a) (c) (d) (e) (f) (g) (h) (i) remark in the 2.7 v/1.59 v poc mode ( option byte: pocmode = 1), the cpu cl ock status changes to (a) in the above figure when the supply voltage exceeds 2.7 v (typ.), and to (b) after reset processing (20 s (typ.)).
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 162 table 6-5 shows transition of the cpu clock and examples of setting the sfr registers. table 6-5. cpu clock transition a nd sfr register setting examples (1/4) (1) cpu operating with internal high-speed oscillation clock (b) a fter reset release (a) status transition sfr register setting (a) (b) sfr registers do not have to be se t (default status after reset release). (2) cpu operating with high-speed system clock (c) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) setting flag of sfr register status transition amph exclk oscsel mstop ostc register xsel mcm0 (a) (b) (c) (x1 clock: 1 mhz f xh 10 mhz) 0 0 1 0 must be checked 1 1 (a) (b) (c) (external main clock: 1 mhz f xh 10 mhz) 0 1 1 0 must not be checked 1 1 (a) (b) (c) (x1 clock: 10 mhz < f xh 20 mhz) 1 0 1 0 must be checked 1 1 (a) (b) (c) (external main clock: 10 mhz < f xh 20 mhz) 1 1 1 0 must not be checked 1 1 caution set the clock after the supply voltage has reached the operable voltage of the clock to be set (see chapter 29 electrical specifications (target)). (3) cpu operating with subsystem cl ock (d) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) setting flag of sfr register status transition xtstart exclks oscsels waiting for oscillation stabilization css 0 0 1 (a) (b) (d) (xt1 clock) 1 necessary 1 (a) (b) (d) (external subsystem clock) 0 1 1 unnecessary 1 remarks 1. (a) to (i) in table 6-5 correspond to (a) to (i) in figure 6-14. 2. exclk, oscsel, exclks, oscsels, amph: bits 7 to 4 and 0 of the clock oper ation mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) xtstart, css: bits 6 and 4 of the processor clock control register (pcc) : don?t care
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 163 table 6-5. cpu clock transition a nd sfr register setting examples (2/4) (4) cpu clock changing from inte rnal high-speed oscillation clock (b) to high-speed system clock (c) (setting sequence of sfr registers) setting flag of sfr register status transition amph note exclk oscsel mstop ostc register xsel note mcm0 (b) (c) (x1 clock: 1 mhz f xh 10 mhz) 0 0 1 0 must be checked 1 1 (b) (c) (external main clock: 1 mhz f xh 10 mhz) 0 1 1 0 must not be checked 1 1 (b) (c) (x1 clock: 10 mhz < f xh 20 mhz) 1 0 1 0 must be checked 1 1 (b) (c) (external main clock: 10 mhz < f xh 20 mhz) 1 1 1 0 must not be checked 1 1 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock note the value of this flag can be changed only once after a re set release. this setting is not necessary if it has already been set. caution set the clock after the supply voltage has reached the operable voltage of the clock to be set (see chapter 29 electrical specifications (target)). (5) cpu clock changing from in ternal high-speed oscillation cl ock (b) to subsystem clock (d) (setting sequence of sfr registers) setting flag of sfr register status transition xtstart exclks oscsels waiting for oscillation stabilization css 0 0 1 (b) (d) (xt1 clock) 1 necessary 1 (b) (d) (external subsystem cl ock) 0 1 1 unnecessary 1 unnecessary if the cpu is operating with the subsystem clock remarks 1. (a) to (i) in table 6-5 correspond to (a) to (i) in figure 6-14. 2. exclk, oscsel, exclks, oscsels, amph: bits 7 to 4 and 0 of the clock oper ation mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) xtstart, css: bits 6 and 4 of the processor clock control register (pcc) : don?t care
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 164 table 6-5. cpu clock transition a nd sfr register setting examples (3/4) (6) cpu clock changing from high- speed system clock (c) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 (c) (b) 0 confirm this flag is 1. 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock (7) cpu clock changing from high-speed system clock (c) to subsystem clock (d) (setting sequence of sfr registers) setting flag of sfr register status transition xtstart exclks oscsels waiting for oscillation stabilization css 0 0 1 (c) (d) (xt1 clock) 1 necessary 1 (c) (d) (external subsystem clock) 0 1 1 unnecessary 1 unnecessary if the cpu is operating with the subsystem clock (8) cpu clock changing from subsystem clock (d ) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 css (d) (b) 0 confirm this flag is 1. 0 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock unnecessary if xsel is 0 remarks 1. (a) to (i) in table 6-5 correspond to (a) to (i) in figure 6-14. 2. mcm0: bit 0 of the main clock mode register (mcm) exclks, oscsels: bits 5 and 4 of the clo ck operation mode select register (oscctl) rsts, rstop: bits 7 and 0 of the internal oscillation mode register (rcm) xtstart, css: bits 6 and 4 of the processor clock control register (pcc) : don?t care
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 165 table 6-5. cpu clock transition a nd sfr register setting examples (4/4) (9) cpu clock changing from subsystem clock (d) to high-sp eed system clock (c) (setting sequence of sfr registers) setting flag of sfr register status transition amph note exclk oscsel mstop ostc register xsel note mcm0 css (d) (c) (x1 clock: 1 mhz f xh 10 mhz) 0 0 1 0 must be checked 1 1 0 (d) (c) (external main clock: 1 mhz f xh 10 mhz 0 1 1 0 must not be checked 1 1 0 (d) (c) (x1 clock: 10 mhz < f xh 20 mhz) 1 0 1 0 must be checked 1 1 0 (d) (c) (external main clock: 10 mhz < f xh 20 mhz) 1 1 1 0 must not be checked 1 1 0 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock unnecessary if this register is already set note the value of this flag can be changed only once after a re set release. this setting is not necessary if it has already been set. caution set the clock after the supply voltage has reached the operable voltage of the clock to be set (see chapter 29 electrical specifications (target)). (10) ? halt mode (e) set while cpu is operating wit h internal high-speed oscillation clock (b) ? halt mode (f) set while cpu is ope rating with high-speed system clock (c) ? halt mode (g) set while cpu is operating with subsystem clock (d) status transition setting (b) (e) (c) (f) (d) (g) executing halt instruction (11) ? stop mode (h) set while cp u is operating with internal hi gh-speed oscillation clock (b) ? stop mode (i) set while cpu is ope rating with high-speed system clock (c) (setting sequence) status transition setting (b) (h) (c) (i) stopping peripheral functions that cannot operate in stop mode executing stop instruction remarks 1. (a) to (i) in table 6-5 correspond to (a) to (i) in figure 6-14. 2. exclk, oscsel, amph: bits 7, 6 and 0 of the clock operation mode sele ct register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc)
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 166 6.6.7 condition before changing cpu clo ck and processing after changing cpu clock condition before changing the cpu clock and processing after changing the cpu clock are shown below. table 6-6. changing cpu clock cpu clock before change after change condition before change processing after change x1 clock stabilization of x1 oscillation ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time internal high- speed oscillation clock external main system clock enabling input of exter nal clock from exclk pin ? mstop = 0, oscsel = 1, exclk = 1 ? internal high-speed oscillator can be stopped (rstop = 1). ? clock supply to cpu is stopped for 5 s (min.) after amph has been set to 1. x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock operating current can be reduced by stopping internal high-speed oscillator (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock xt1 clock stabilization of xt1 oscillation ? xtstart = 0, exclks = 0, oscsels = 1, or xtstart = 1 ? after elapse of oscillation stabilization time external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock operating current can be reduced by stopping internal high-speed oscillator (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock external subsystem clock enabling input of ex ternal clock from exclks pin ? xtstart = 0, exclks = 1, oscsels = 1 external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock ? rstop = 0, mcs = 0 xt1 oscillation can be stopped or external subsystem clock input can be disabled (oscsels = 0). x1 clock stabilization of x1 oscillation and selection of high-speed system cl ock as main system clock ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time ? mcs = 1 xt1 clock, external subsystem clock external main system clock enabling input of exter nal clock from exclk pin and selection of high-speed system clock as main system clock ? mstop = 0, oscsel = 1, exclk = 1 ? mcs = 1 ? xt1 oscillation can be stopped or external subsystem clock input can be disabled (oscsels = 0). ? clock supply to cpu is stopped for 5 s (min.) after amph has been set to 1.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 167 6.6.8 time required for switchover of cpu clock and main system clock by setting bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc), the cpu clock can be switched (between the main system clock and the s ubsystem clock) and the division ratio of the main system clock can be changed. the actual switchover operat ion is not performed immediately after rewr iting to pcc; operat ion continues on the pre-switchover clock for several clocks (see table 6-7 ). whether the cpu is oper ating on the main system clock or the sub system clock can be ascertained using bit 5 (cls) of the pcc register. table 6-7. time required for switchover of cpu clock and main system cl ock cycle division factor set value before switchover set value after switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks 2f xp /f sub clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks f xp /f sub clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks f xp /2f sub clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks f xp /4f sub clocks 0 1 0 0 1 clock 1 clock 1 clock 1 clock f xp /8f sub clocks 1 2 clocks 2 clocks 2 clo cks 2 clocks 2 clocks caution selection of the main system clock cycle division factor (pcc0 to pcc2) and switchover from the main system clock to th e subsystem clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possi ble, however, for selection of th e main system cl ock cycle division factor (pcc0 to pcc2) and switchover from th e subsystem clock to th e main system clock (changing css from 1 to 0). remarks 1. the number of clocks listed in table 6-7 is the number of cpu clocks before switchover. 2. when switching the cpu clock from the subsystem clock to the main system clock, calculate the number of clocks by rounding up to the next clo ck and discarding the decimal portion, as shown below. example when switching cpu clock from f sub /2 to f xp /2 (@ oscillation with f sub = 32.768 khz, f xp = 10 mhz) f xp /f sub = 10000/32.768 ? 305.1 306 clocks by setting bit 0 (mcm0) of the main clock mode register (mcm), the main system clo ck can be switch ed (between the internal high-speed oscillation clock and the high-speed system clock). the actual switchover oper ation is not performed immediately after re writing to mcm0; operation continues on the pre-switchover clock for several clocks (see table 6-8 ). whether the cpu is operating on the internal high-speed oscillation cloc k or the high-speed system clock can be ascertained using bit 1 (mcs) of mcm.
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 168 table 6-8. maximum time required for main system clock switchover set value before switchover set value after switchover mcm0 mcm0 0 1 0 1 + 2f rh /f xh clock 1 1 + 2f xh /f rh clock caution when switching the intern al high-speed oscillation clock to the high-speed system clock, bit 2 (xsel) of mcm must be set to 1 in advance. the value of xsel can be changed only once after a reset release. remarks 1. the number of clocks listed in table 6-8 is t he number of main system clocks before switchover. 2. calculate the number of clocks in t able 6-8 by removing the decimal portion. example when switching the main system clock from the internal high-speed oscillation clock to the high-speed system clock (@ oscillation with f rh = 8 mhz, f xh = 10 mhz) 1 + 2f rh /f xh = 1 + 2 8/10 = 1 + 2 0.8 = 1 + 1.6 = 2.6 2 clocks 6.6.9 conditions before cl ock oscillation is stopped the following lists the register flag settings for stopping th e clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. table 6-9. conditions before the clo ck oscillation is stopped and flag settings clock conditions before clock oscillation is stopped (external clock input disabled) flag settings of sfr register internal high-speed oscillation clock mcs = 1 or cls = 1 (the cpu is operating on a clock ot her than the internal high-speed oscillation clock) rstop = 1 x1 clock external main system clock mcs = 1 or cls = 1 (the cpu is operating on a clock other than the high-speed system clock) mstop = 1 xt1 clock external subsystem clock cls = 0 (the cpu is operating on a clock other than the subsystem clock) oscsels = 0
chapter 6 clock generator preliminary user?s manual u17260ej3v1ud 169 6.6.10 peripheral hardware and source clocks the following lists peripheral hardware and source clocks incorpor ated in the 78k0/ke2. table 6-10. peripheral ha rdware and source clocks source clock peripheral hardware peripheral hardware clock (f prs ) subsystem clock (f sub ) internal low- speed oscillation clock (f rl ) tm50 output external clock from peripheral hardware pins 00 y n n n y (ti000 pin) note 16-bit timer/ event counter 01 y n n n y (ti001 pin) note 50 y n n n y (ti50 pin) note 8-bit timer/ event counter 51 y n n n y (ti51 pin) note h0 y n n y n 8-bit timer h1 y n y n n watch timer y y n n n watchdog timer n n y n n buzzer output y n n n n clock output y y n n n a/d converter y n n n n uart0 y n n y n uart6 y n n y n csi10 y n n n y (sck10 pin) note csi11 y n n n y (sck11 pin) note serial interface iic0 y n n n y (exscl0, scl0 pin) note note when the cpu is operating on the s ubsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of thes e functions on the external clock input from peripheral hardware pins. remark y: can be selected, n: cannot be selected
preliminary user?s manual u17260ej3v1ud 170 chapter 7 16-bit timer/even t counters 00 and 01 the pd78f0531, 78f0532, and 78f0533 incorporate 16-bit timer/ event counter 00, and the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d incorpor ate 16-bit timer/event counters 00 and 01. 7.1 functions of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 note have the following functions. (1) interval timer 16-bit timer/event counters 00 and 01 generate an in terrupt request at the preset time interval. (2) square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (3) external event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (4) one-shot pulse output 16-bit timer event counters 00 and 01 can output a one-sh ot pulse whose output pulse width can be set freely. (5) ppg output 16-bit timer/event counters 00 and 01 can output a recta ngular wave whose frequency and output pulse width can be set freely. (6) pulse width measurement 16-bit timer/event counters 00 and 01 can measure th e pulse width of an externally input signal. note available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 171 7.2 configuration of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. table 7-1. configuration of 16- bit timer/event counters 00 and 01 item configuration time/counter 16-bit timer counter 0n (tm0n) register 16-bit timer capture/compare registers 00n, 01n (cr00n, cr01n) timer input ti00n, ti01n pins timer output to0n pin, output controller control registers 16-bit timer mode control register 0n (tmc0n) 16-bit timer capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 0 (pm0) port register 0 (p0) remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d figures 7-1 and 7-2 show the block diagrams. figure 7-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p01 f prs f prs /2 2 f prs /2 8 f prs ti000/p00 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ p01 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 output latch (p01) pm01 to cr010
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 172 figure 7-2. block diagram of 16-bit timer/event counter 01 (available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d) internal bus capture/compare control register 01 (crc01) ti011/to01/p06 f prs f prs /2 4 f prs /2 6 f prs ti001/p05/ ssi11 prescaler mode register 01 (prm01) 2 prm011 prm010 crc012 16-bit timer capture/compare register 011 (cr011) match match 16-bit timer counter 01 (tm01) clear noise elimi- nator crc012 crc011 crc010 inttm001 to01/ti011/ p06 inttm011 16-bit timer output control register 01 (toc01) 16-bit timer mode control register 01 (tmc01) internal bus tmc013 tmc012 tmc011 ovf01 toc014 lvs01 lvr01 toc011 toe01 selector 16-bit timer capture/compare register 001 (cr001) selector selector selector noise elimi- nator noise elimi- nator output controller ospe01 ospt01 output latch (p06) pm06 to cr011 (1) 16-bit timer counter 0n (tm0n) tm0n is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. if the count value is read during operat ion, then input of the count clock is temporarily stopped, and the count value at that point is read. figure 7-3. format of 16-bit timer counter 0n (tm0n) tm0n (n = 0, 1) ff11h (tm00), ffb1h (tm01) ff10h (tm00), ffb0h (tm01) address: ff10h, ff11h (tm00), ffb0h, ffb1h (tm01) after reset: 0000h r 1514131211109876543210 remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f053 6, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 173 the count value of tm0n can be read by reading tm0n when the value of bits 3 and 2 (tmc0n3 and tmc0n2) of 16-bit timer mode control register 0n (tmc0n) is other th an 00. the value of tm0n is 0000h if it is read when tmc0n3 and tmc0n2 = 00. the count value is reset to 0000h in the following cases. ? at reset signal generation ? if tmc0n3 and tmc0n2 are cleared to 00 ? if the valid edge of the ti00n pin is input in the mode in which the clear & start occurs when inputting the valid edge to the ti00n pin ? if tm0n and cr00n match in the mode in which the clear & start occurs when tm0n and cr00n match ? ospt0n is set to 1 in one-shot pulse output m ode or the valid edge is input to the ti00n pin cautions 1. even if tm0n is read , the value is not captured by cr01n. 2. when tm0n is read, input of the count clo ck is temporarily stopped a nd it is resumed after the timer has been read. th erefore, no clock miss occurs. (2) 16-bit timer capture/compare regi ster 00n (cr00n)), 16-bit timer captu re/compare register 01n (cr01n) cr00n and cr01n are 16-bit registers that are used with a capture function or compar ison function selected by using crc0n. change the value of cr00n while the timer is stopped (tmc0n3 and tmc0n2 = 00). the value of cr01n can be changed during operation if the val ue has been set in a specific way. for details, see 7.5.1 rewriting cr01n during tm0n operation . these registers can be read or written in 16-bit units. reset signal generation sets these registers to 0000h. figure 7-4. format of 16-bit timer ca pture/compare register 00n (cr00n) cr00n (n = 0, 1) ff13h (cr000), ffb3h (cr001) ff12h (cr000), ffb2h (cr001) address: ff12h, ff13h (cr000), ffb2h, ffb3h (cr001) after reset: 0000h r/w 1514131211109876543210 remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 174 (i) when cr00n is used as a compare register the value set in cr00n is constantly compared with the tm0n count value, and an interrupt request signal (inttm00n) is generated if they match. t he value is held until cr00n is rewritten. (ii) when cr00n is used as a capture register the count value of tm0n is captured to cr00n when a capture trigger is input. as the capture trigger, an edge of a phas e reverse to that of the ti00n pin or the valid edge of the ti01n pin can be selected by using crc0n or prm0n. figure 7-5. format of 16-bit timer ca pture/compare register 01n (cr01n) cr01n (n = 0, 1) ff15h (cr010), ffb5h (cr011) ff14h (cr010), ffb4h (cr011) address: ff14h, ff15h (cr010), ffb4h, ffb5h (cr011) after reset: 0000h r/w 1514131211109876543210 (i) when cr01n is used as a compare register the value set in cr01n is constantly compared with the tm0n count value, and an interrupt request signal (inttm01n) is generated if they match. (ii) when cr01n is used as a capture register the count value of tm0n is captured to cr01n when a capture trigger is input. it is possible to select the valid edge of the ti00n pin as the capture trigger. the ti00n pin valid edge is set by prm0n. cautions 1. to use this regist er as a compare register, set a val ue other than 0000h to cr00n and cr01n. 2. the valid edge of ti010 and timer output (t o00) cannot be used for the p01 pin at the same time, and the valid edge of ti 011 and timer output (to01) cannot be used for the p06 pin at the same time. select ei ther of the functions. 3. if clearing of its 3 and 2 (tmc0n3 and tmc0 n2) of 16-bit timer mode control register 0n (tmc0n) to 00 and input of the capture trigger c onflict, then the capture d data is undefined. 4. to change the mode from the capture mode to the comparis on mode, first clear the tmc0n3 and tmc0n2 bits to 00, and then change the setting. a value that has been once captured remains stored in cr 00n unless the device is reset. if the mode has been changed to the comparis on mode, be sure to set a comparison value. 5. cr00n/cr01n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 175 table 7-2. capture oper ation of cr00n and cr01n external input signal capture operation ti00n pin input ti01n pin input set values of es0n1 and es0n0 position of edge to be captured set values of es1n1 and es1n0 position of edge to be captured 01: rising 01: rising 00: falling 00: falling crc0n1 = 1 ti00n pin input (reverse phase) 11: both edges (cannot be captured) crc0n1 bit = 0 ti01n pin input 11: both edges capture operation of cr00n interrupt signal inttm00n signal is not generated even if value is captured. interrupt signal inttm00n signal is generated each time value is captured. set values of es0n1 and es0n0 position of edge to be captured 01: rising 00: falling ti00n pin input note 11: both edges capture operation of cr01n interrupt signal inttm01n signal is generated each time value is captured. note the capture operation of cr01n is not affected by the setting of the crc0n1 bit. caution to capture the count value of the tm0n regi ster to the cr00n regist er by using the phase reverse to that input to the ti 00n pin, the interrupt request si gnal (inttm00n) is not generated after the value has been captured . if the valid edge is detect ed on the ti01n pin during this operation, the capture operation is not performe d but the inttm00n signal is generated as an external interrupt signal. to not use the external interrupt, mask the inttm00n signal. remarks 1. crc0n1: see 7.3 (2) capture/compare control register 0n (crc0n) . es1n1, es1n0, es0n1, es0n0: see 7.3 (4) prescaler mode register 0n (prm0n) . 2. n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f05 36, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 176 7.3 registers controlling 16-bi t timer/event counters 00 and 01 registers used to control 16-bit timer/ event counters 00 and 01 are shown below. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare contro l register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) ? port mode register 0 (pm0) ? port register 0 (p0) (1) 16-bit timer mode cont rol register 0n (tmc0n) tmc0n is an 8-bit register that sets the 16-bit time r/event counter 0n operation mode, tm0n clear mode, and output timing, and detects an overflow. rewriting tmc0n is prohibited during operation (when tm c0n3 and tmc0n2 = other than 00). however, it can be changed when tmc0n3 and tmc0n2 are cleared to 00 (s topping operation) and when ovf0n is cleared to 0. tmc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets tmc0n to 00h. caution 16-bit timer/event counter 0n starts operation at the moment tmc0n2 and tmc0n3 are set to values other than 00 (operation stop mode), resp ectively. set tmc0n2 and tmc0n3 to 00 to stop the operation. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 177 figure 7-6. format of 16-bit timer mode control register 00 (tmc00) address: ffbah after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc00 0 0 0 0 tmc003 tmc002 tmc001 ovf00 tmc003 tmc002 operation enable of 16-bit timer/event counter 00 0 0 disables tm00 operation. stops supplying operating clock. asynchronously resets the internal circuit. 0 1 free-running timer mode 1 0 clear & start mode entered by ti000 pin valid edge input note 1 1 clear & start mode entered upon a match between tm00 and cr000 tmc001 condition to reverse timer output (to00) 0 ? match between tm00 and cr000 or match between tm00 and cr010 1 ? match between tm00 and cr000 or match between tm00 and cr010 ? trigger input of ti000 pin valid edge ovf00 tm00 overflow flag clear (0) clears ovf00 to 0 or tmc003 and tmc002 = 00 set (1) overflow occurs. ovf00 is set to 1 when the value of tm00 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti000 pin valid edge input, and clear & start mode entered upon a match between tm00 and cr000). it can also be set to 1 by writing 1 to ovf00. note the ti000 pin valid edge is set by bits 5 and 4 ( es001, es000) of prescaler mode register 00 (prm00).
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 178 figure 7-7. format of 16-bit timer mode control register 01 (tmc01) address: ffb6h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc01 0 0 0 0 tmc013 tmc012 tmc011 ovf01 tmc013 tmc012 operation enable of 16-bit timer/event counter 01 0 0 disables tm01 operation. stops supplying operating clock. asynchronously resets the internal circuit. 0 1 free-running timer mode 1 0 clear & start mode entered by ti001 pin valid edge input note 1 1 clear & start mode entered upon a match between tm01 and cr001 tmc011 condition to reverse timer output (to01) 0 ? match between tm01 and cr001 or match between tm01 and cr011 1 ? match between tm01 and cr001 or match between tm01 and cr011 ? trigger input of ti001 pin valid edge ovf01 tm01 overflow flag clear (0) clears ovf01 to 0 or tmc013 and tmc012 = 00 set (1) overflow occurs. ovf01 is set to 1 when the value of tm01 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti001 pin valid edge input, and clear & start mode entered upon a match between tm01 and cr001). it can also be set to 1 by writing 1 to ovf01. note the ti001 pin valid edge is set by bits 5 and 4 ( es011, es010) of prescaler mode register 01 (prm01).
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 179 (2) capture/compare control register 0n (crc0n) crc0n is the register that controls the operation of cr00n and cr01n. changing the value of crc0n is prohibited during oper ation (when tmc0n3 and tmc0n2 = other than 00). crc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears crc0n to 00h. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d figure 7-8. format of capture/comp are control register 00 (crc00) address: ffbch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 pin 1 captures on valid edge of ti000 pin by reverse phase note the valid edge of the ti010 and ti000 pin is set by prm00. if es001 and es000 are set to 11 (both edges) when crc001 is 1, the valid edge of the ti000 pin cannot be detected. crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register if tmc003 and tmc002 are set to 11 (clear & start mode entered upon a match between tm00 and cr000), be sure to set crc000 to 0. note when the valid edge is detected from the ti010 pin, the capture opera tion is not performed but the inttm000 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perf ormed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (prm00).
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 180 figure 7-9. example of cr01n capture op eration (when rising edge is specified) count clock tm0n ti00n rising edge detection cr01n inttm01n n ? 3n ? 2n ? 1 n n + 1 n valid edge remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d figure 7-10. format of capture/comp are control register 01 (crc01) address: ffb8h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc01 0 0 0 0 0 crc012 crc011 crc010 crc012 cr011 operating mode selection 0 operates as compare register 1 operates as capture register crc011 cr001 capture trigger selection 0 captures on valid edge of ti011 pin 1 captures on valid edge of ti001 pin by reverse phase note the valid edge of the ti011 and ti001 pin is set by prm01. if es011 and es010 are set to 11 (both edges) when crc011 is 1, the valid edge of the ti001 pin cannot be detected. crc010 cr001 operating mode selection 0 operates as compare register 1 operates as capture register if tmc013 and tmc012 are set to 11 (clear & start mode entered upon a match between tm01 and cr001), be sure to set crc010 to 0. note when the valid edge is detected from the ti011 pin, the capture opera tion is not performed but the inttm001 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perf ormed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by pr escaler mode register 01 (prm01) (see figure 7-9 example of cr01n capture oper ation (when rising edge is specified).
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 181 (3) 16-bit timer output control register 0n (toc0n) toc0n is an 8-bit register that controls the to0n pin output. toc0n can be rewritten while only ospt0n is oper ating (when tmc0n3 and tmc0n2 = other than 00). rewriting the other bits is prohibited during operation. however, toc0n4 can be rewritten during timer operation as a means to rewrite cr01n (see 7.5.1 rewriting cr01n during tm0n operation ). toc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears toc0n to 00h. caution be sure to set toc0n using the following procedure. <1> set toc0n4 and toc0n1 to 1. <2> set only toe0n to 1. <3> set either of lvs0n or lvr0n to 1. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 182 figure 7-11. format of 16-bit timer ou tput control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always ?0? when it is read. do not set this bit to 1 in a mode other than the one- shot pulse output mode. if it is set to 1, tm00 is cleared and started. ospe00 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti000 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm00 and cr000. toc004 to00 pin output control on match between cr010 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm010) is generated even when toc004 = 0. lvs00 lvr00 setting of to00 pin output status 0 0 no change 0 1 initial value of to00 pin output is low level (to00 pin output is cleared to 0). 1 0 initial value of to00 pin output is high level (to00 pin output is set to 1). 1 1 setting prohibited ? lvs00 and lvr00 can be used to set the initial value of the output level of the to00 pin. if the initial value does not have to be set, leave lvs00 and lvr00 as 00. ? be sure to set lvs00 and lvr00 when toe00 = 1. lvs00, lvr00, and toe00 being simultaneously set to 1 is prohibited. ? lvs00 and lvr00 are trigger bits. by setting these bits to 1, the initial value of the output level of the to00 pin can be set. even if these bits are clear ed to 0, output of the to00 pin is not affected. ? the values of lvs00 and lvr00 are always 0 when they are read. ? for how to set lvs00 and lvr00, see 7.5.2 setting lvs0n and lvr0n . toc001 to00 pin output control on match between cr000 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm000) is generated even when toc001 = 0. toe00 to00 pin output control 0 disables output (to00 pin output fixed to low level) 1 enables output
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 183 figure 7-12. format of 16-bit timer ou tput control register 01 (toc01) address: ffb9h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc01 0 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 ospt01 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always 0 w hen it is read. do not set this bit to 1 in a mode other than the one-shot pulse output mode. if it is set to 1, tm01 is cleared and started. ospe01 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti001 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm01 and cr001. toc014 to01 pin output control on match between cr011 and tm01 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm011) is generated even when toc014 = 0. lvs01 lvr01 setting of to01 pin output status 0 0 no change 0 1 initial value of to01 pin output is low level (to01 pin output is cleared to 0). 1 0 initial value of to01 pin output is high level (to01 pin output is set to 1). 1 1 setting prohibited ? lvs01 and lvr01 can be used to set the initial value of the output level of the to01 pin. if the initial value does not have to be set, leave lvs01 and lvr01 as 00. ? be sure to set lvs01 and lvr01 when toe01 = 1. lvs01, lvr01, and toe01 being simultaneously set to 1 is prohibited. ? lvs01 and lvr01 are trigger bits. by setting these bits to 1, the initial value of the output level of the to01 pin can be set. even if these bits are clear ed to 0, output of the to01 pin is not affected. ? the values of lvs01 and lvr01 are always 0 when they are read. ? for how to set lvs01 and lvr01, see 7.5.2 setting lvs0n and lvr0n . toc011 to01 pin output control on match between cr001 and tm01 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm001) is generated even when toc011 = 0. toe01 to01 pin output control 0 disables output (to01 pin output is fixed to low level) 1 enables output
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 184 (4) prescaler mode register 0n (prm0n) prm0n is the register that se ts the tm0n count clock and ti00n and ti01n pin input valid edges. rewriting prm0n is prohibited during operati on (when tmc0n3 and tmc0n2 = other than 00). prm0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets prm0n to 00h. cautions 1. do not apply the following setting wh en setting the prm0n1 and prm0n0 bits to 11 (to specify the valid edge of th e ti00n pin as a count clock). ? clear & start mode entered by the ti00n pin valid edge ? setting the ti00n pin as a capture trigger 2. if the operation of the 16- bit timer/event counter 0n is enab led when the ti00n or ti01n pin is at high level and when the va lid edge of the ti00n or ti01n pi n is specified to be the rising edge or both edges, the high level of the ti00n or ti01n pin is detected as a rising edge. note this when the ti00n or ti01n pin is pulle d up. however, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. 3. the valid edge of ti010 and timer output (to 00) cannot be used for the p01 pin at the same time, and the valid edge of ti 011 and timer output (to01) cannot be used for the p06 pin at the same time. select ei ther of the functions. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 185 figure 7-13. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection prm001 prm000 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 f prs 2 mhz 5 mhz 10 mhz 20 mhz 0 1 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 78.12 khz 1 1 ti000 valid edge note note the external clock requires a pulse two cycles longer than internal clock (f prs ). remark f prs : peripheral hardware clock frequency
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 186 figure 7-14. format of prescaler mode register 01 (prm01) address: ffb7h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm01 es111 es110 es011 es010 0 0 prm011 prm010 es111 es110 ti011 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es011 es010 ti001 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection prm011 prm010 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 f prs 2 mhz 5 mhz 10 mhz 20 mhz 0 1 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 1 0 f prs /2 6 31.25 khz 78.125 khz 156.25 khz 312.5 khz 1 1 ti001 valid edge note note the external clock requires a pulse two cycles longer than internal clock (f prs ). remark f prs : peripheral hardware clock frequency
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 187 (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p01/to00/ti010 and p 06/to01/ti011 pins for timer outpu t, set pm01 and pm06 and the output latches of p01 and p06 to 0. when using the p00/ti000, p01/to00/ ti010, p05/ti001/ssi11, and p06/to01/ti011 pins for timer input, set pm00, pm01, pm05, and pm06 to 1. at this time, the output latches of p00, p01, p05, and p06 may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm0 to ffh. figure 7-15. format of port mode register 0 (pm0) 7 1 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 6) output mode (output buffer on) input mode (output buffer off)
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 188 7.4 operation of 16-bit ti mer/event counters 00 and 01 7.4.1 interval timer operation if bits 3 and 2 (tmc0n3 and tmc0n2) of the 16-bit timer mode co ntrol register (tmc0n) are set to 11 (clear & start mode entered upon a match between tm0n and cr00n), the count operation is started in synchronization with the count clock. when the value of tm0n later matches the value of cr00n, tm0n is cleared to 0000h and a match interrupt signal (inttm00n) is generated. this inttm00n signal ena bles tm0n to operate as an interval timer. remarks 1. for the setting of i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . figure 7-16. block diagram of interval timer operation 16-bit counter (tm0n) cr00n register operable bits tmc0n3, tmc0n2 count clock clear match signal inttm00n signal figure 7-17. basic timing exampl e of interval timer operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match interrupt (inttm00n) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 189 figure 7-18. example of register se ttings for interval timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n) 00000 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) if m is set to cr00n, the interval time is as follows. ? interval time = (m + 1) count clock cycle setting cr00n to 0000h is prohibited. (g) 16-bit capture/compare register 01n (cr01n) usually, cr01n is not used for the interval timer func tion. however, a compare match interrupt (inttm01n) is generated when the set value of cr01n matches the value of tm0n. therefore, mask the interrupt request by using the interrupt mask flag (tmmk01n). remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 190 figure 7-19. example of software pr ocessing for interval timer function tm0n register 0000h operable bits (tmc0n3, tmc0n2) cr00n register inttm00n signal n 11 00 n n n <1> <2> tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, cr00n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 191 7.4.2 square wave output operation when 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1 ), a square wave can be output from the to0n pin by setting the 16-bit timer output control register 0n (toc0n) to 03h. when tmc0n3 and tmc0n2 are set to 11 (count clear & start mode entered upon a match between tm0n and cr00n), the counting operation is started in synchronizat ion with the count clock. when the value of tm0n later matches the value of cr00n, tm0n is cleared to 0000h, an interrupt signal (inttm00n) is generated, and output of th e to0n pin is inverted. this to0n pi n output that is inverted at fixed intervals enables to0n to output a square wave. remarks 1. for the setting of i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 19 interrupt functions . figure 7-20. block diagram of square wave output operation 16-bit counter (tm0n) cr00n register operable bits tmc0n3, tmc0n2 count clock clear match signal inttm00n signal output controller to0n pin remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d figure 7-21. basic timing example of square wave output operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) to0n pin output compare match interrupt (inttm00n) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 192 figure 7-22. example of register setti ngs for square wave output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n pin output. inverts to0n pin output on match between tm0n and cr00n. 011 (d) prescaler mode register 0n (prm0n) 00000 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) if m is set to cr00n, the interval time is as follows. ? square wave frequency = 1 / [2 (m + 1) count clock cycle] setting cr00n to 0000h is prohibited. (g) 16-bit capture/compare register 01n (cr01n) usually, cr01n is not used for the square wave outpu t function. however, a compare match interrupt (inttm01n) is generated when the set valu e of cr01n matches the value of tm0n. therefore, mask the interrupt request by using the interrupt mask flag (tmmk01n). remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 193 figure 7-23. example of software proce ssing for square wave output function tm0n register 0000h operable bits (tmc0n3, tmc0n2) cr00n register to0n pin output inttm00n signal to0n output control bit (toe0n) n 11 00 n n n <1> <2> tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, toc0n register note , cr00n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 194 7.4.3 external event counter operation when bits 1 and 0 (prm0n1 and prm0n0) of the prescaler m ode register 0n (prm0n) are set to 11 (for counting up with the valid edge of the ti00n pin) and bits 3 and 2 (tmc0n3 and tmc0n2) of 16-bit timer mode control register 0n (tmc0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between tm0n and cr00n (inttm00n) is generated. to input the external event, the ti00n pin is used. th erefore, the timer/event co unter cannot be used as an external event counter in the clear & start mode enter ed by the ti00n pin valid edge input (when tmc0n3 and tmc0n2 = 10). the inttm00n signal is generated with the following timing. ? timing of generation of inttm00n signal (second time or later) = number of times of detection of valid edge of external event (set value of cr00n + 1) however, the first match interrupt immediately after the timer/event counter has start ed operating is generated with the following timing. ? timing of generation of inttm00n signal (first time only) = number of times of detection of valid edge of external event input (set value of cr00n + 2) to detect the valid edge, the signal input to t he ti00n pin is sampled during the clock cycle of f prs . the valid edge is not detected until it is detected two times in a row. t herefore, a noise with a short pul se width can be eliminated. remarks 1. for the setting of i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 19 interrupt functions . figure 7-24. block diagram of ex ternal event counter operation 16-bit counter (tm0n) cr00n register operable bits tmc0n3, tmc0n2 clear match signal inttm00n signal f prs edge detection ti00n pin output controller to0n pin remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 195 figure 7-25. example of register setti ngs in external event counter mode (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n) 0 0 0/1 0/1 0 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock (specifies valid edge of ti00n). 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 011 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) if m is set to cr00n, the interrupt signal (inttm00n) is generated when the num ber of external events reaches (m + 1). setting cr00n to 0000h is prohibited. (g) 16-bit capture/compare register 01n (cr01n) usually, cr01n is not used in the external event counter mode. however, a compare match interrupt (inttm01n) is generated when the set valu e of cr01n matches the value of tm0n. therefore, mask the interrupt request by using the interrupt mask flag (tmmk01n). remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 196 figure 7-26. example of software proce ssing in external event counter mode tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match signal (inttm00n) n 11 00 n n n <1> <2> tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, cr00n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 197 7.4.4 operation in clear & start mode entered by ti00n pin valid edge input when bits 3 and 2 (tmc0n3 and tmc0n2) of 16-bit timer mode control register 0n (tmc0n) are set to 10 (clear & start mode entered by the ti00n pin va lid edge input) and the count clock (set by prm0n) is supplied to the timer/event counter, tm0n starts counti ng up. when the valid edge of the ti 00n pin is detected during the counting operation, tm0n is cleared to 0000h a nd starts counting up again. if the valid edge of the ti00n pin is not detected, tm0n overflows and continues counting. the valid edge of the ti00n pin is a c ause to clear tm0n. starting the counter is not controlled immediately after the start of the operation. cr00n and cr01n are used as compare registers and capture registers. (a) when cr00n and cr01n ar e used as compare registers signals inttm00n and inttm01n are generated when the va lue of tm0n matches the value of cr00n and cr01n. (b) when cr00n and cr01n ar e used as capture registers the count value of tm0n is captur ed to cr00n and the inttm00n signal is generated when the valid edge is input to the ti01n pin (or when the phase reverse to that of the valid edge is input to the ti00n pin). when the valid edge is input to t he ti00n pin, the count value of tm0n is captured to cr01n and the inttm01n signal is generated. as soon as the count value has been captured, t he counter is cleared to 0000h. caution do not set the count clock as the valid edge of the ti00n pin (prm0n1 and prm0n0 = 11). when prm0n1 and prm0n0 = 11, tm0n is cleared. remarks 1. for the setting of the i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 19 interrupt functions . 3. n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 198 (1) operation in clear & start mode en tered by ti00n pin valid edge input (cr00n: compare register , cr01n: compare register) figure 7-27. block diagram of clear & start mode entered by ti00n pin valid edge input (cr00n: compare register , cr01n: compare register) timer counter (tm0n) clear output controller edge detection compare register (cr01n) match signal to0n pin match signal interrupt signal (inttm00n) interrupt signal (inttm01n) ti00n pin compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 199 figure 7-28. timing example of clear & star t mode entered by ti00n pin valid edge input (cr00n: compare register , cr01n: compare register) (a) toc0n = 13h, prm0n = 10h, crc0n, = 00h, tmc0n = 08h tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0 n pin output m 10 m nn nn mmm 00 n (b) toc0n = 13h, prm0n = 10h, crc0n, = 00h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n pin output m 10 m nn nn mmm 00 n (a) and (b) differ as follows depending on the setting of bit 1 (tmc0n1) of the 16-bit timer mode control register 0n (tmc0n). (a) the output level of the to0n pin is inve rted when tm0n matches a compare register. (b) the output level of the to0n pin is inverted wh en tm0n matches a compare register or when the valid edge of the ti00n pin is detected. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 200 (2) operation in clear & start mode en tered by ti00n pin valid edge input (cr00n: compare register , cr01n: capture register) figure 7-29. block diagram of clear & start mode entered by ti00n pin valid edge input (cr00n: compare register, cr01n: capture register) timer counter (tm0n) clear output controller edge detector capture register (cr01n) capture signal to0n pin match signal interrupt signal (inttm00n) interrupt signal (inttm01n) ti00n pin compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 201 figure 7-30. timing example of clear & star t mode entered by ti00n pin valid edge input (cr00n: compare register, cr01n: capture register) (1/2) (a) toc0n = 13h, prm0n = 10h, crc0n, = 04h, tmc0n = 08h, cr00n = 0001h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) to0n pin output 0001h 10 q p n m s 00 0000h m n s p q this is an application example where the output level of the to0n pin is inverted when the count value has been captured & cleared. the count value is captured to cr01n and tm0n is cleared (to 0000h) when the valid edge of the ti00n pin is detected. when the count value of tm0n is 0001h, a compare match interr upt signal (inttm00n) is generated, and the output level of t he to0n pin is inverted. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 202 figure 7-30. timing example of clear & star t mode entered by ti00n pin valid edge input (cr00n: compare register, cr01n: capture register) (2/2) (b) toc0n = 13h, prm0n = 10h, crc0n, = 04h, tmc0n = 0ah, cr00n = 0003h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) to0n pin output 0003h 0003h 10 q p n m s 00 0000h m 4444 ns pq this is an application exampl e where the width set to cr0 0n (4 clocks in this example) is to be output from the to0n pin when the count value has been captured & cleared. the count value is captured to cr01n, a capture interr upt signal (inttm01n) is gener ated, tm0n is cleared (to 0000h), and the output level of the to0n pin is inverted when the valid e dge of the ti00n pin is detected. when the count value of tm0n is 0003h (four clocks have b een counted), a compare match interrupt signal (inttm00n) is generated and the output level of the to0n pin is inverted. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 203 (3) operation in clear & start mode by entered ti00n pin valid edge input (cr00n: capture register , cr01n: compare register) figure 7-31. block diagram of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: compare register) timer counter (tm0n) clear output controller edge detection capture register (cr00n) capture signal to0n pin match signal interrupt signal (inttm01n) interrupt signal (inttm00n) ti00n pin compare register (cr01n) operable bits tmc0n3, tmc0n2 count clock remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 204 figure 7-32. timing example of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: compare register) (1/2) (a) toc0n = 13h, prm0n = 10h, crc0n, = 03h, tmc0n = 08h, cr01n = 0001h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) capture register (cr00n) capture interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n pin output 10 p n m s 00 l 0001h 0000h mns p this is an application example where the output level of the to0n pin is to be inverted when the count value has been captured & cleared. tm0n is cleared at the rising edge det ection of the ti00n pin and it is captured to cr00n at the falling edge detection of the ti00n pin. when bit 1 (crc0n1) of capture/compare control register 0n (crc0n) is set to 1, the count value of tm0n is captured to cr00n in the phase reverse to that of the signa l input to the ti00n pin, but the capture interrupt signal (inttm00n) is not generated. however, the inttm00n sig nal is generated when the valid edge of the ti01n pin is detected. mask the inttm00n signal when it is not used. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 205 figure 7-32. timing example of clear & star t mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: compare register) (2/2) (b) toc0n = 13h, prm0n = 10h, crc0n, = 03h, tmc0n = 0ah, cr01n = 0003h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) to0n pin output 0003h 0003h 10 p n m s 00 4444 l 0000h m n s p this is an application exampl e where the width set to cr0 1n (4 clocks in this example) is to be output from the to0n pin when the count value has been captured & cleared. tm0n is cleared (to 0000h) at the rising edge detection of the ti00n pin and captur ed to cr00n at the falling edge detection of the ti00n pin. t he output level of the to0n pin is inve rted when tm0n is cleared (to 0000h) because the rising edge of the ti00n pin has been detected or when the va lue of tm0n matches that of a compare register (cr01n). when bit 1 (crc0n1) of capture/compare control register 0n (crc0n) is 1, the count value of tm0n is captured to cr00n in the phase reverse to that of the input si gnal of the ti00n pin, but th e capture interrupt signal (inttm00n) is not generated. however, the inttm00n inte rrupt is generated when t he valid edge of the ti01n pin is detected. mask the inttm00n signal when it is not used. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 206 (4) operation in clear & start mode en tered by ti00n pin valid edge input (cr00n: capture register , cr01n: capture register) figure 7-33. block diagram of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: capture register) timer counter (tm0n) clear output controller capture register (cr00n) capture signal capture signal to0n pin note interrupt signal (inttm01n) interrupt signal (inttm00n) capture register (cr01n) operable bits tmc0n3, tmc0n2 count clock edge detection ti00n pin edge detection ti01n pin note selector note the timer output (to0n) cannot be used when det ecting the valid edge of the ti01n pin is used. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 207 figure 7-34. timing example of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: capture register) (1/3) (a) toc0n = 13h, prm0n = 30h , crc0n = 05h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) capture register (cr00n) capture interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) to0n pin output 10 r s t o l m n p q 00 l 0000h 0000h lm nopqrst this is an application example wher e the count value is captured to cr0 1n, tm0n is cleared, and the to0n pin output is inverted when the rising or fal ling edge of the ti00n pin is detected. when the edge of the ti01n pin is det ected, an interrupt signal (inttm00n) is generated. mask the inttm00n signal when it is not used. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 208 figure 7-34. timing example of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: capture register) (2/3) (b) toc0n = 13h, prm0n = c0h, crc0n = 05h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti01n pin input) capture register (cr00n) capture interrupt (inttm00n) capture & count clear input (ti00n) capture register (cr01n) capture interrupt (inttm01n) 10 r s t o l m n p q 00 ffffh l l 0000h 0000h lmn o pq r s t this is a timing example where an edge is not input to the ti00n pin, in an applicatio n where the count value is captured to cr00n when the rising or fa lling edge of the ti01n pin is detected. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 209 figure 7-34. timing example of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: capture register) (3/3) (c) toc0n = 13h, prm0n = 00h , crc0n = 07h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) capture register (cr00n) capture register (cr01n) capture interrupt (inttm01n) capture input (ti01n) compare match interrupt (inttm00n) 0000h 10 p o m q r t s w n l 00 l l ln r pt 0000h moq sw this is an application example where the pulse width of the signal input to the ti00n pin is measured. by setting crc0n, the count value can be captured to cr00n in the phase reverse to the falling edge of the ti00n pin (i.e., rising edge) and to cr01n at the falling edge of the ti00n pin. the high- and low-level widths of the input pulse can be calculated by the following expressions. ? high-level width = [cr01n value] ? [cr00n value] [count clock cycle] ? low-level width = [cr00n value] [count clock cycle] if the reverse phase of the ti00n pin is selected as a tri gger to capture the count value to cr00n, the inttm00n signal is not generated. read the values of cr00n an d cr01n to measure the pulse width immediately after the inttm01n signal is generated. however, if the valid edge specified by bits 6 and 5 (e s1n1 and es1n0) of prescaler mode register 0n (prm0n) is input to the ti01n pin, the count value is not captured but the inttm00 n signal is generated. to measure the pulse width of the ti00n pin, mask the inttm00n signal when it is not used. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 210 figure 7-35. example of register settings in clear & st art mode entered by ti00n pin valid edge input (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000100/10 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts at valid edge input of ti00n pin. 0: inverts to0n output on match between cr00n and cr01n. 1: inverts to0n output on match between cr00n and cr01n and valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 000000/10/10/1 crc0n2 crc0n1 crc0n0 0: cr00n used as compare register 1: cr00n used as capture register 0: cr01n used as compare register 1: cr01n used as capture register 0: ti01n pin is used as capture trigger of cr00n. 1: reverse phase of ti00n pin is used as capture trigger of cr00n. (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output note 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr00n/cr01n. 01: inverts to0n output on match between tm0n and cr00n. 10: inverts to0n output on match between tm0n and cr01n. 11: inverts to0n output on match between tm0n and cr00n/cr01n. specifies initial value of to0n output f/f 0/1 0/1 0/1 note the timer output (to0n) cannot be used when det ecting the valid edge of the ti01n pin is used. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 211 figure 7-35. example of register settings in clear & st art mode entered by ti00n pin valid edge input (2/2) (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 count clock selection (setting ti00n valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc0n1 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) when this register is used as a compare register an d when its value matches the count value of tm0n, an interrupt signal (inttm00n) is generated. the count value of tm0n is not cleared. to use this register as a capture regist er, select either the ti00n or ti01n pin note input as a capture trigger. when the valid edge of the capture tr igger is detected, the count va lue of tm0n is stored in cr00n. note the timer output (to0n) cannot be used when detection of the vali d edge of the ti01n pin is used. (g) 16-bit capture/compare register 01n (cr01n) when this register is used as a compare register an d when its value matches the count value of tm0n, an interrupt signal (inttm01n) is generated. the count value of tm0n is not cleared. when this register is used as a capt ure register, the ti00n pi n input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of tm0n is stored in cr01n. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 212 figure 7-36. example of software processing in clear & start mode entered by ti 00n pin valid edge input tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n pin output m 10 m n n n n mmm 00 <1> <2> <2> <2> <3> <2> 00 n tmc0n3, tmc0n2 bits = 10 edge input to ti00n pin register initial setting prm0n register, crc0n register, toc0 n register note , cr00n, cr01n registers, tmc0n.tmc0n1 bit, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 10. starts count operation when the valid edge is input to the ti00n pin, the value of the tm0n register is cleared. start <1> count operation start flow <2> tm0n register clear & start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 213 7.4.5 free-running timer operation when bits 3 and 2 (tmc0n3 and tmc0n2) of 16-bit timer mode control register 0n (t mc0n) are set to 01 (free- running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock. when it has counted up to ffffh, the over flow flag (ovf0n) is set to 1 at t he next clock, and tm0n is cleared (to 0000h) and continues counting. clear ovf0n to 0 by executing the clr instruction via software. the following three types of free-runn ing timer operations are available. ? both cr00n and cr01n are used as compare registers. ? one of cr00n or cr01n is used as a compare regi ster and the other is us ed as a capture register. ? both cr00n and cr01n are used as capture registers. remarks 1. for the setting of the i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 19 interrupt functions . (1) free-running timer mode operation (cr00n: compare register , cr01n: compare register) figure 7-37. block diagram of free-running timer mode (cr00n: compare register, cr01n: compare register) timer counter (tm0n) output controller compare register (cr01n) match signal to0n pin match signal interrupt signal (inttm00n) interrupt signal (inttm01n) compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 214 figure 7-38. timing example of free-running timer mode (cr00n: compare register, cr01n: compare register) ? toc0n = 13h, prm0n = 00h, crc0n = 00h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n pin output ovf0n bit 01 m n m n m n m n 00 00 n 0 write clear 0 write clear 0 write clear 0 write clear m this is an application example where two compare registers are used in the free-running timer mode. the output level of t he to0n pin is reversed each time the count value of tm0n matches the set value of cr00n or cr01n. when the count value matches the register value, the inttm00n or inttm01n signal is generated. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d (2) free-running timer mode operation (cr00n: compare register , cr01n: capture register) figure 7-39. block diagram of free-running timer mode (cr00n: compare register, cr01n: capture register) timer counter (tm0n) output controller edge detection capture register (cr01n) capture signal to0n pin match signal interrupt signal (inttm00n) interrupt signal (inttm01n) ti00n pin compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 215 figure 7-40. timing example of free-running timer mode (cr00n: compare register, cr01n: capture register) ? toc0n = 13h, prm0n = 10h, crc0n = 04h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) capture interrupt (inttm01n) to0n pin output overflow flag (ovf0n) 01 m n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h 0001h mn s p q this is an application example where a compare register an d a capture register are used at the same time in the free-running timer mode. in this example, the inttm00n signal is generated and the output level of the to0n pin is reversed each time the count value of tm0n matches the set value of cr00n (com pare register). in addition, the inttm01n signal is generated and the count value of tm0n is captured to cr01n each time the valid edge of the ti00n pin is detected. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 216 (3) free-running timer mode operation (cr00n: capture register , cr01n: capture register) figure 7-41. block diagram of free-running timer mode (cr00n: capture register, cr01n: capture register) timer counter (tm0n) capture register (cr00n) capture signal capture signal interrupt signal (inttm01n) interrupt signal (inttm00n) capture register (cr01n) operable bits tmc0n3, tmc0n2 count clock edge detection ti00n pin edge detection ti01n pin selector remarks 1. if both cr00n and cr01n are used as capture regi sters in the free-running timer mode, the output level of the to0n pin is not inverted. however, it can be inverted each time the valid edge of the ti00n pin is detected if bit 1 (tmc0n1) of 16-bit timer mode control register 0n (tmc0n) is set to 1. 2. n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 217 figure 7-42. timing example of free-running timer mode (cr00n: capture register, cr01n: capture register) (1/2) (a) toc0n = 13h, prm0n = 50h, crc0n = 05h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) capture register (cr01n) capture interrupt (inttm01n) capture trigger input (ti01n) capture register (cr00n) capture interrupt (inttm00n) overflow flag (ovf0n) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q this is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stor ed in separate capture registers in the free-running timer mode. the count value is captured to cr01n when the valid edge of the ti00n pi n input is detected and to cr00n when the valid edge of the ti01n pin input is detected. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 218 figure 7-42. timing example of free-running timer mode (cr00n: capture register, cr01n: capture register) (2/2) (b) toc0n = 13h, prm0n = c0h, crc0n = 05h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti01n) capture register (cr00n) capture interrupt (inttm00n) capture trigger input (ti00n) capture register (cr01n) capture interrupt (inttm01n) 01 l m p s n o r q t 00 0000h 0000h lmn o pq r s t l l this is an application example wh ere both the edges of the ti01n pin ar e detected and the count value is captured to cr00n in the free-running timer mode. when both cr00n and cr01n are used as capture register s and when the valid edge of only the ti01n pin is to be detected, the count value cannot be captured to cr01n. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 219 figure 7-43. example of register setti ngs in free-running timer mode (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000010/10 tmc0n3 tmc0n2 tmc0n1 ovf0n free-running timer mode 0: inverts to0n pin output on match between cr00n and cr01n. 1: inverts to0n pin output on match between cr00n and cr01n and valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 000000/10/10/1 crc0n2 crc0n1 crc0n0 0: cr00n used as compare register 1: cr00n used as capture register 0: cr01n used as compare register 1: cr01n used as capture register 0: ti01n pin is used as capture trigger of cr00n. 1: reverse phase of ti00n pin is used as capture trigger of cr00n. (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr00n/cr01n. 01: inverts to0n output on match between tm0n and cr00n. 10: inverts to0n output on match between tm0n and cr01n. 11: inverts to0n output on match between tm0n and cr00n/cr01n. specifies initial value of to0n output f/f 0/1 0/1 0/1 remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 220 figure 7-43. example of register setti ngs in free-running timer mode (2/2) (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 count clock selection (setting ti00n valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc0n1 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) when this register is used as a compare register an d when its value matches the count value of tm0n, an interrupt signal (inttm00n) is generated. the count value of tm0n is not cleared. to use this register as a capture register, select ei ther the ti00n or ti01n pin in put as a capture trigger. when the valid edge of the capture tr igger is detected, the count va lue of tm0n is stored in cr00n. (g) 16-bit capture/compare register 01n (cr01n) when this register is used as a compare register an d when its value matches the count value of tm0n, an interrupt signal (inttm01n) is generated. the count value of tm0n is not cleared. when this register is used as a capt ure register, the ti00n pi n input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of tm0n is stored in cr01n. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 221 figure 7-44. example of software pr ocessing in free-running timer mode ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) timer output control bits (toe0n, toc0n4, toc0n1) to0n pin output m 01 n n n n m m m 00 <1> <2> 00 n tmc0n3, tmc0n2 bits = 0, 1 register initial setting prm0n register, crc0n register, toc0n register note , cr00n/cr01n register, tmc0n.tmc0n1 bit, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 01. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 0, 0 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <2> count operation stop flow note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 222 7.4.6 ppg output operation a square wave having a pulse width set in advance by cr01n is output from the to0n pin as a ppg (programmable pulse generator) signal during a cycle set by cr00n when bits 3 and 2 (tmc0n3 and tmc0n2) of 16- bit timer mode control register 0n (tmc0n) are set to 11 (clear & start upon a match between tm0n and cr00n). the pulse cycle and duty factor of the pulse generated as the ppg output are as follows. ? pulse cycle = (set value of cr00n + 1) count clock cycle ? duty = (set value of cr01n + 1) / (set value of cr00n + 1) caution to change the duty factor ( value of cr01n) during operation, see 7.5.1 rewriting cr01n during tm0n operation. remarks 1. for the setting of i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 19 interrupt functions . figure 7-45. block diagram of ppg output operation timer counter (tm0n) clear output controller compare register (cr01n) match signal to0n pin match signal interrupt signal (inttm00n) interrupt signal (inttm01n) compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 223 figure 7-46. example of register settings for ppg output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register cr01n used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output 11: inverts to0n output on match between tm0n and cr00n/cr01n. 00: disables one-shot pulse output specifies initial value of to0n output f/f 0/1 1 1 (d) prescaler mode register 0n (prm0n) 00000 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) an interrupt signal (inttm00n) is generated when the value of this register matches the count value of tm0n. the count value of tm0n is not cleared. (g) 16-bit capture/compare register 01n (cr01n) an interrupt signal (inttm01n) is generated when the value of this register matches the count value of tm0n. the count value of tm0n is not cleared. caution set values to cr00n and cr01n such that the condition 0000h < cr01n < cr00n ffffh is satisfied. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 224 figure 7-47. example of software pr ocessing for ppg output operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) timer output control bits (toe0n, toc0n4, toc0n1) to0n pin output n 11 m m m n n n 00 <1> n + 1 <2> 00 m tmc0n3, tmc0n2 bits = 11 register initial setting prm0n register, crc0n register, toc0n register note , cr00n, cr01n registers, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <2> count operation stop flow n + 1 n + 1 m + 1 m + 1 m + 1 note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remarks 1. ppg pulse cycle = (m + 1) count clock cycle ppg duty = (n + 1)/(m + 1) 2. n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 225 7.4.7 one-shot pulse output operation a one-shot pulse can be output by setting bits 3 and 2 (tmc0n3 and tmc0n2) of the 16-bit timer mode control register 0n (tmc0n) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the ti00n pin valid edge) and setting bit 5 (ospe0n) of 16-bit timer ou tput control register 0n (toc0n) to 1. when bit 6 (ospt0n) of toc0n is set to 1 or when the valid edge is input to the ti00n pin during timer operation, clearing & starting of tm0n is triggered, and a pulse of the difference between the values of cr00n and cr01n is output only once from the to0n pin. cautions 1. do not input the trigger again (setting ospt0n to 1 or detecting th e valid edge of the ti00n pin) while the one-shot pulse is output. to out put the one-shot pulse again, generate the trigger after the current one-s hot pulse output has completed. 2. to use only the setting of ospt0n to 1 as the trigger of one-shot pulse output, do not change the level of the ti00n pin or its alternate func tion port pin. othe rwise, the pulse will be unexpectedly output. remarks 1. for the setting of the i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 19 interrupt functions . figure 7-48. block diagram of on e-shot pulse output operation timer counter (tm0n) output controller compare register (cr01n) match signal to0n pin match signal interrupt signal (inttm00n) interrupt signal (inttm01n) compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock ti00n edge detection ospt0n bit ospe0n bit clear remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 226 figure 7-49. example of register settings for one-shot pulse output operation (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000/10/100 tmc0n3 tmc0n2 tmc0n1 ovf0n 01: free running timer mode 10: clear and start mode by valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register cr01n used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0/1 1 1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n pin output inverts to0n output on match between tm0n and cr00n/cr01n. specifies initial value of to0n pin output enables one-shot pulse output software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). 0/1 1 1 (d) prescaler mode register 0n (prm0n) 00000 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 227 figure 7-49. example of register settings for one-shot pulse output operation (2/2) (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) this register is used as a compar e register when a one-shot pulse is output. when the value of tm0n matches that of cr00n, an interrupt signal (inttm00n) is generated and t he output level of the to0n pin is inverted. (g) 16-bit capture/compare register 01n (cr01n) this register is used as a compar e register when a one-shot pulse is output. when the value of tm0n matches that of cr01n, an interrupt signal (inttm01n) is generated and t he output level of the to0n pin is inverted. caution do not set identical val ues or 0000h for cr0n0 and cr0n1. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 228 figure 7-50. example of software processing for one-shot pulse output operation (1/2) ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) one-shot pulse enable bit (ospen) one-shot pulse trigger bit (osptn) one-shot pulse trigger input (ti00n pin) overflow plug (ovf0n) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n pin output to0n output control bits (toe0n, toc0n4, toc0n1) n m n ? m n ? m 01 or 10 00 00 n n n m m m m + 1 m + 1 <1> <2> <2> <3> to0n output level is not inverted because no one- shot trigger is input. ? time from when the one-shot pulse trigger is input until the one-shot pulse is output = (m + 1) count clock cycle ? one-shot pulse output active level width = (n ? m) count clock cycle remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 229 figure 7-50. example of software processing for one-shot pulse output operation (2/2) tmc0n3, tmc0n2 bits = 01 or 10 register initial setting prm0n register, crc0n register, toc0n register note , cr00n, cr01n registers, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow <2> one-shot trigger input flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow toc0n.ospt0n bit = 1 or edge input to ti00n pin write the same value to the bits other than the ostp0n bit. note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 230 7.4.8 pulse width measurement operation tm0n can be used to measure the pulse width of the signal input to the ti00n and ti01n pins. measurement can be accomplished by operating the 16-bit ti mer/event counter 0n in the free-running timer mode or by restarting the timer in synchronizati on with the signal input to the ti00n pin. when an interrupt is generated, read the value of the valid capture register and measure the pulse width. check bit 0 (ovf0n) of 16-bit timer mode control register 0n (tmc 0n). if it is set (to 1), clear it to 0 by software. figure 7-51. block di agram of pulse width measureme nt (free-running timer mode) timer counter (tm0n) capture register (cr00n) capture signal capture signal interrupt signal (inttm01n) interrupt signal (inttm00n) capture register (cr01n) operable bits tmc0n3, tmc0n2 count clock edge detection ti00n pin edge detection ti01n pin selector remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d figure 7-52. block diagram of pulse width measurement (clear & start mode entered by ti00n pin valid edge input) timer counter (tm0n) capture register (cr00n) capture signal capture signal interrupt signal (inttm01n) interrupt signal (inttm00n) capture register (cr01n) operable bits tmc0n3, tmc0n2 count clock edge detection ti00n pin edge detection ti01n pin clear selector remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 231 a pulse width can be measured in the following three ways. ? measuring the pulse width by using two input signals of the ti00n and ti01n pins (free-running timer mode) ? measuring the pulse width by using one input signal of the ti00n pin (free-running timer mode) ? measuring the pulse width by using one input signal of the ti00n pin (clear & start mode entered by the ti00n pin valid edge input) remarks 1. for the setting of the i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 19 interrupt functions . 3. n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f05 36, 78f0537, 78f0537d (1) measuring the pulse width by using two input sign als of the ti00n and ti01n pins (free-running timer mode) set the free-running timer mode (tmc0n3 and tmc0n2 = 01). when the valid edge of t he ti00n pin is detected, the count value of tm0n is captured to cr01n. when the valid edge of the ti 01n pin is detected, the count value of tm0n is captured to cr00n. specify detecti on of both the edges of the ti00n and ti01n pins. by this measurement method, the prev ious count value is subt racted from the count valu e captured by the edge of each input signal. therefore, sa ve the previously captured value to a separate register in advance. if an overflow occurs, the value becomes negative if the pr eviously captured value is si mply subtracted from the current captured value and, t herefore, a borrow occurs (bit 0 (cy) of the program status word (psw) is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear bit 0 (ovf0n) of 16-bit timer mode control register 0n (tmc0n) to 0.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 232 figure 7-53. timing example of pulse width measurement (1) ? tmc0n = 04h, prm0n = f0h, crc0n = 05h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) capture register (cr01n) capture interrupt (inttm01n) capture trigger input (ti01n) capture register (cr00n) capture interrupt (inttm00n) overflow flag (ovf0n) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 233 (2) measuring the pulse width by using one input signal of the ti00n pin (free-running mode) set the free-running timer mode (tmc0n3 and tmc0n2 = 01). the count value of tm0n is captured to cr00n in the phase reverse to the valid edge detec ted on the ti00n pin. when the valid edge of the ti00n pin is detected, the count value of tm0n is captured to cr01n. by this measurement method, values are stored in se parate capture registers when a width from one edge to another is measured. theref ore, the capture values do not have to be saved. by subtracting the value of one capture register from that of a nother, a high-level width, low-level width, and cycle are calculated. if an overflow occurs, the value becomes negative if one c aptured value is simply subtracted from another and, therefore, a borrow occurs (bit 0 (cy) of the program status word (psw) is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addi tion, clear bit 0 (ovf0n) of 16-bit timer mode control register 0n (tmc0n) to 0. figure 7-54. timing example of pulse width measurement (2) ? tmc0n = 04h, prm0n = 10h, crc0n = 07h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) capture register (cr00n) capture register (cr01n) capture interrupt (inttm01n) overflow flag (ovf0n) capture trigger input (ti01n) compare match interrupt (inttm00n) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h l l abc d e 0000h mn s p q remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 234 (3) measuring the pulse width by using one input signal of the ti00n pin (clear & st art mode entered by the ti00n pin valid edge input) set the clear & start mode entered by the ti00n pin valid edge (tmc0n3 and tmc0n2 = 10). the count value of tm0n is captured to cr00n in the phase reverse to the valid edge of the ti00n pin, and the count value of tm0n is captured to cr01n and tm0n is cleared (0000h) when t he valid edge of the ti00n pin is detected. therefore, a cycle is stored in cr01n if tm0n does not overflow. if an overflow occurs, take the value that results from adding 10000h to the value stored in cr01n as a cycle. clear bit 0 (ovf0n) of 16-bit timer mode control register 0n (tmc0n) to 0. figure 7-55. timing example of pulse width measurement (3) ? tmc0n = 08h, prm0n = 10h, crc0n = 07h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n) capture register (cr00n) capture register (cr01n) capture interrupt (inttm01n) overflow flag (ovf0n) capture trigger input (ti01n) capture interrupt (inttm00n) 10 <1> <2> <3> <3> <3> <3> <2> <2> <2> <1> <1> <1> m a b cd n s p q 00 00 0 write clear 0000h l l abc d 0000h mn s p q <1> pulse cycle = (10000h number of times ovf0n bit is set to 1 + captured value of cr01n) count clock cycle <2> high-level pulse width = (10000h number of times ovf0n bit is set to 1 + captured value of cr00n) count clock cycle <3> low-level pulse width = (pulse cycle ? high-level pulse width) remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 235 figure 7-56. example of register setti ngs for pulse width measurement (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000/10/100 tmc0n3 tmc0n2 tmc0n1 ovf0n 01: free running timer mode 10: clear and start mode entered by valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 0000010/11 crc0n2 crc0n1 crc0n0 1: cr00n used as capture register 1: cr01n used as capture register 0: ti01n pin is used as capture trigger of cr00n. 1: reverse phase of ti00n pin is used as capture trigger of cr00n. (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock (setting valid edge of ti00n is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting when crc0n1 = 1 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 236 figure 7-56. example of register setti ngs for pulse width measurement (2/2) (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) this register is used as a capture register. either th e ti00n or ti01n pin is selected as a capture trigger. when a specified edge of t he capture trigger is detec ted, the count value of tm0n is stored in cr00n. (g) 16-bit capture/compare register 01n (cr01n) this register is used as a capture register. the signal input to the ti 00n pin is used as a capture trigger. when the capture trigger is detected, the count value of tm0n is stored in cr01n. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 237 figure 7-57. example of software proce ssing for pulse width measurement (1/2) (a) example of free-running timer mode ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) capture register (cr01n) capture interrupt (inttm01n) capture trigger input (ti01n) capture register (cr00n) capture interrupt (inttm00n) 01 d 00 d 00 d 01 d 01 d 02 d 02 d 03 d 03 d 04 d 04 d 10 d 10 d 11 d 11 d 12 d 12 d 13 d 13 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> (b) example of clear & start mode entered by ti00n pin valid edge ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n) capture register (cr00n) capture interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) 10 d 0 l d 0 d 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <3> <2> remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 238 figure 7-57. example of software proce ssing for pulse width measurement (2/2) <2> capture trigger input flow edge detection of ti00n, ti01n pins calculated pulse width from capture value stores count value to cr00n, cr01n registers generates capture interrupt note tmc0n3, tmc0n2 bits = 01 or 10 register initial setting prm0n register, crc0n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow note the capture interrupt signal (in ttm00n) is not generated when the reve rse-phase edge of the ti00n pin input is selected to the valid edge of cr00n. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 239 7.5 special use of tm0n 7.5.1 rewriting cr01n during tm0n operation in principle, rewriting cr00n and cr01n of the 78k0/ke2 when they are used as compare registers is prohibited while tm0n is operating (tmc0n3 and tmc0n2 = other than 00). however, the value of cr01n can be changed, even while tm0n is operating, using the following procedure if cr01n is used for ppg output and the duty factor is chang ed (change the value of cr01n immediately after its value matches the value of tm0n. if t he value of cr01n is changed immediatel y before its value matches tm0n, an unexpected operation may be performed). procedure for changing value of cr01n <1> disable interrupt inttm01n (tmmk01n = 1). <2> disable reversal of the timer output when th e value of tm0n matches that of cr01n (toc0n4 = 0). <3> change the value of cr01n. <4> wait for one cycle of the count clock of tm0n. <5> enable reversal of the timer output when the value of tm0n matches that of cr01n (toc0n4 = 1). <6> clear the interrupt flag of inttm01n (tmif01n = 0) to 0. <7> enable interrupt inttm01n (tmmk01n = 0). remark for tmif01n and tmmk01n, see chapter 19 interrupt functions . 7.5.2 setting lvs0n and lvr0n (1) usage of lvs0n and lvr0n lvs0n and lvr0n are used to set the default value of the to0n pin output and to inve rt the timer output without enabling the timer operation (tmc0n3 and tmc0n2 = 00). clear lvs0n and lvr0n to 00 (default value: low- level output) when software control is unnecessary. lvs0n lvr0n timer output status 0 0 not changed (low-level output) 0 1 cleared (low-level output) 1 0 set (high-level output) 1 1 setting prohibited remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 240 (2) setting lvs0n and lvr0n set lvs0n and lvr0n using the following procedure. figure 7-58. example of flow for setting lvs0n and lvr0n bits setting toc0n.ospe0n, toc0n4, toc0n1 bits setting toc0n.toe0n bit setting toc0n.lvs0n, lvr0n bits setting tmc0n.tmc0n3, tmc0n2 bits <3> enabling timer operation <2> setting of timer output f/f <1> setting of timer output operation caution be sure to set lvs0n and lvr0n fo llowing steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. figure 7-59. timing example of lvr0n and lvs0n toc0n.lvs0n bit toc0n.lvr0n bit operable bits (tmc0n3, tmc0n2) to0n pin output inttm00n signal <1> 00 <2> <1> <3> <4> <4> <4> 01, 10, or 11 <1> the to0n pin output goes high when lvs0n and lvr0n = 10. <2> the to0n pin output goes low when lvs0n and lv r0n = 01 (the pin output remains unchanged from the high level even if lvs0n and lvr0n are cleared to 00). <3> the timer starts operating when tmc0n3 and tmc0n2 are set to 01, 10, or 11. because lvs0n and lvr0n were set to 10 before the operat ion was started, the to 0n pin output starts from the high level. after the timer starts operating, setting lvs0n and lvr0n is prohibited until tmc0n3 and tmc0n2 = 00 (disabling the timer operation). <4> the output level of the to0n pi n is inverted each time an interrupt signal (inttm00n) is generated. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 241 7.6 cautions for 16-bit timer/event counters 00 and 01 (1) restrictions for each channel of 16-bit timer/event counter 0n table 7-5 shows the restrictions for each channel. table 7-5. restrictions for each ch annel of 16-bit timer/event counter 0n operation restriction as interval timer as square wave output ? as external event counter toc0n = 00h as clear & start mode entered by ti00n pin valid edge input using timer output (to0n) is prohibited when det ection of the valid edge of the ti01n pin is used. toc0n = 00h as free-running timer ? as ppg output setting identical values or 0000h to cr00n and cp01n is prohibited. as one-shot pulse output ? as pulse width measurement toc0n = 00h (2) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because counting tm0n is start ed asynchronously to the count pulse. figure 7-60. start timing of tm0n count 0000h timer start 0001h 0002h 0003h 0004h count pulse tm0n count value (3) setting of cr00n and cr01n (c lear & start mode entered upon a match between tm0n and cr00n) set a value other than 0000h to cr00n and cr01n (tm0n c annot count one pulse when it is used as an external event counter). remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 242 (4) timing of holding data by capture register (a) when the valid edge is input to t he ti00n/ti01n pin and the reverse phase of the ti00n pin is detected while cr00n/cr01n is read, cr01n performs a capture operation but the read value of cr00n/cr01n is not guaranteed. at this time, an interrupt signal (inttm 00n/inttm01n) is generated wh en the valid edge of the ti00n/ti01n pin is detected (t he interrupt signal is not generated when the reverse-phase edge of the ti00n pin is detected). when the count value is captured because the valid edge of the ti00n/ti01n pi n was detected, read the value of cr00n/cr01n after inttm00n/inttm01n is generated. figure 7-61. timing of holding data by capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm0n count value edge input inttm01n value captured to cr01n capture read signal capture operation is performed but read value is not guaranteed. capture operation (b) the values of cr00n and cr01n are not guarant eed after 16-bit timer/event counter 0n stops. (5) setting valid edge set the valid edge of the ti00n pin while the timer operation is stopped (tmc0n3 and tmc0n2 = 00). set the valid edge by using es0n0 and es0n1. (6) re-triggering one-shot pulse make sure that the trigger is not generated while an active level is being output in t he one-shot pulse output mode. be sure to input the next trigger afte r the current active level is output. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 243 (7) operation of ovf0n flag (a) setting ovf0n flag (1) the ovf0n flag is set to 1 in the following case, as well as when tm0n overflows. select the clear & start mode entered upon a match between tm0n and cr00n. set cr00n to ffffh. when tm0n matches cr00n and tm0n is cleared from ffffh to 0000h figure 7-62. operation timing of ovf0n flag fffeh ffffh ffffh 0000h 0001h count pulse tm0n inttm00n ovf0n cr00n (b) clearing ovf0n flag even if the ovf0n flag is cleared to 0 after tm0n overflows and before the next count clock is counted (before the value of tm0n becomes 0001h), it is set to 1 again and clearing is invalid. (8) one-shot pulse output one-shot pulse output operates correct ly in the free-running timer mode or the clear & start mode entered by the ti00n pin valid edge. the one-shot pulse cannot be output in the clea r & start mode entered upon a match between tm0n and cr00n. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u17260ej3v1ud 244 (9) capture operation (a) when valid edge of ti00n is specified as count clock when the valid edge of ti00n is specified as the count cl ock, the capture register for which ti00n is specified as a trigger does not operate correctly. (b) pulse width to accurately capture value by signals input to ti01n and ti00n pins to accurately capture the count value, the pulse input to the ti00n and ti01n pins as a capture trigger must be wider than two count clocks selected by prm0n (see figure 7-9 ). (c) generation of interrupt signal the capture operation is per formed at the falling edge of the count clock but the in terrupt signals (inttm00n and inttm01n) are generated at the risi ng edge of the next count clock (see figure 7-9 ). (d) note when crc0n1 (bit 1 of capture/compa re control register 0n (crc0n)) is set to 1 when the count value of the tm0n regist er is captured to the cr00n regi ster in the phase reverse to the signal input to the ti00n pin, the interrupt signal (i nttm00n) is not generated after the count value is captured. if the valid edge is det ected on the ti01n pin during this oper ation, the captur e operation is not performed but the inttm00n signal is generated as an ex ternal interrupt signal. mask the inttm00n signal when the external interrupt is not used. (10) edge detection (a) specifying valid edge after reset if the operation of the 16-bit timer/ev ent counter 0n is enabled after reset and while the ti00n or ti01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the ti00n or ti01n pin, then the high level of the ti00n or ti01n pin is detected as the rising edge. note this when the ti00n or ti01n pin is pulled up. however, t he rising edge is not detected when the operation is once stopped and then enabled again. (b) sampling clock for eliminating noise the sampling clock for eliminating noise differs depend ing on whether the valid edge of ti00n is used as the count clock or capture trigger. in the fo rmer case, the sampling clock is fixed to f prs . in the latter, the count clock selected by prm0n is used for sampling. when the signal input to the ti00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. therefore, noise having a short pulse width can be eliminated (see figure 7-9 ). (11) timer operation the signal input to the ti00n/ti01n pin is not acknow ledged while the timer is stopped, regardless of the operation mode of the cpu. remarks 1. f prs : peripheral hardware clock frequency 2. n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
preliminary user?s manual u17260ej3v1ud 245 chapter 8 8-bit timer/even t counters 50 and 51 8.1 functions of 8-bit ti mer/event counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output 8.2 configuration of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. table 8-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to5n control registers timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 1 (pm1) or port mode register 3 (pm3) port register 1 (p1) or port register 3 (p3) figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 246 figure 8-1. block diagram of 8-bit timer/event counter 50 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p17 f prs /2 13 f prs f prs /2 match mask circuit ovf 3 clear tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector to tmh0 to uart0 to uart6 inttm50 to50/ti50/ p17 note 1 note 2 selector 8-bit timer counter 50 (tm50) selector output latch (p17) pm17 f prs /2 2 f prs /2 8 f prs /2 6 figure 8-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 51 (cr51) ti51/to51/ p33/intp4 f prs /2 12 f prs f prs /2 match mask circuit ovf 3 clear tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r s q r inv selector inttm51 to51/ti51/ p33/intp4 note 1 note 2 selector 8-bit timer counter 51 (tm51) selector output latch (p33) pm33 f prs /2 6 f prs /2 4 f prs /2 8 notes 1. timer output f/f 2. pwm output f/f
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 247 (1) 8-bit timer counter 5n (tm5n) tm5n is an 8-bit register that count s the count pulses and is read-only. the counter is incremented in synchronization with the rising edge of the count clock. figure 8-3. format of 8-bit timer counter 5n (tm5n) symbol tm5n (n = 0, 1) address: ff16h (tm50), ff1fh (tm51) after reset: 00h r in the following situations, the count value is cleared to 00h. <1> reset signal generation <2> when tce5n is cleared <3> when tm5n and cr5n match in the mode in which clear & start occurs upon a match of the tm5n and cr5n. (2) 8-bit timer compare register 5n (cr5n) cr5n can be read and written by an 8-bi t memory manipulation instruction. except in pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (in ttm5n) is generated if they match. in the pwm mode, the to5n pin becomes inactive when th e values of tm5n and cr5n ma tch, but no interrupt is generated. the value of cr5n can be set within 00h to ffh. reset signal generation sets cr5n to 00h. figure 8-4. format of 8-bit time r compare register 5n (cr5n) symbol cr5n (n = 0, 1) address: ff17h (cr50), ff41h (cr51) after reset: 00h r/w cautions 1. in the mode in which clear & start oc curs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. 2. in pwm mode, make the cr5n rewrite peri od 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 248 8.3 registers controlling 8-bit ti mer/event counters 50 and 51 the following four registers are used to co ntrol 8-bit timer/event counters 50 and 51. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) ? port mode register 1 (pm1) or port mode register 3 (pm3) ? port register 1 (p1) or port register 3 (p3) (1) timer clock selecti on register 5n (tcl5n) this register sets the count clock of 8-bit timer/ev ent counter 5n and the valid edge of the ti5n pin input. tcl5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets tcl5n to 00h. remark n = 0, 1 figure 8-5. format of timer clo ck selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 count clock selection tcl502 tcl501 tcl500 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 ti50 pin falling edge 0 0 1 ti50 pin rising edge 0 1 0 f prs 2 mhz 5 mhz 10 mhz 20 mhz 0 1 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 1 0 0 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 78.13 khz 1 1 1 f prs /2 13 0.24 khz 0.61 khz 1.22 khz 2.44 khz cautions 1. when rewriting tcl50 to othe r data, stop the timer operation beforehand. 2. be sure to clea r bits 3 to 7 to 0. remark f prs : peripheral hardware clock frequency
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 249 figure 8-6. format of timer clo ck selection register 51 (tcl51) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 count clock selection tcl512 tcl511 tcl510 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 ti51 pin falling edge 0 0 1 ti51 pin rising edge 0 1 0 f prs 2 mhz 5 mhz 10 mhz 20 mhz 0 1 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 1 0 0 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 78.13 khz 1 1 1 f prs /2 12 0.49 khz 1.22 khz 2.44 khz 4.88 khz cautions 1. when rewriting tcl51 to othe r data, stop the timer operation beforehand. 2. be sure to clea r bits 3 to 7 to 0. remark f prs : peripheral hardware clock frequency
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 250 (2) 8-bit timer mode control register 5n (tmc5n) tmc5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> timer output f/f (flip flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode. <5> timer output control tmc5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark n = 0, 1 figure 8-7. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 mode in which clear & start occurs on a match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f clear (0) (default output value of to50 pin: low level) 1 0 timer output f/f set (1) (default ou tput value of to50 pin: high level) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe50 timer output control 0 output disabled (tm50 output is low level) 1 output enabled note bits 2 and 3 are write-only. ( cautions and remarks are listed on the next page.)
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 251 figure 8-8. format of 8-bit timer mode control register 51 (tmc51) address: ff43h after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc51 tce51 tmc516 0 0 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc516 tm51 operating mode selection 0 mode in which clear & start occurs on a match between tm51 and cr51 1 pwm (free-running) mode lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f clear (0) (default output value of to51 pin: low) 1 0 timer output f/f set (1) (default output value of to51 pin: high) 1 1 setting prohibited in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) tmc511 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe51 timer output control 0 output disabled (tm51 output is low level) 1 output enabled note bits 2 and 3 are write-only. cautions 1. the settings of lvs5n and lv r5n are valid in other than pwm mode. 2. perform <1> to <4> below in the following order, not at the same time. <1> set tmc5n1, tmc5n6 : operation mode setting <2> set toe5n to enable output: timer output enable <3> set lvs5n, lvr5n (see caution 1): timer f/f setting <4> set tce5n 3. stop operation befo re rewriting tmc5n6. remarks 1. in pwm mode, pwm output is made inactive by clearing tce5n to 0. 2. if lvs5n and lvr5n are read, the value is 0. 3. the values of the tmc5n6, lvs5n, lvr5n, tmc 5n1, and toe5n bits are re flected at the to5n pin regardless of the value of tce5n. 4. n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 252 (3) port mode registers 1 and 3 (pm1, pm3) these registers set port 1 and 3 input/output in 1-bit units. when using the p17/to50/ti50 and p 33/to51/ti51/intp4 pins for timer output, clear pm17 and pm33 and the output latches of p17 and p33 to 0. when using the p17/to50/ti50 and p33/ to51/ti51/intp4 pins for timer input, set pm17 and pm33 to 1. the output latches of p17 and p33 at this time may be 0 or 1. pm1 and pm3 can be set by a 1-bit or 8- bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 8-9. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 8-10. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 253 8.4 operations of 8-bit timer/event counters 50 and 51 8.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval time r that generates interrupt req uests repeatedly at intervals of the count value preset to 8-bi t timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) ma tches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). setting <1> set the registers. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, se lect the mode in which clear & start occurs on a match of tm5n and cr5n. (tmc5n = 0000 0b = don?t care) <2> after tce5n = 1 is set, the count operation starts. <3> if the values of tm5n and cr5n match, intt m5n is generated (tm5n is cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. set tce5n to 0 to stop the count operation. caution do not write other values to cr5n during operation. remarks 1. for how to enable the inttm5n signal interrupt, see chapter 19 interrupt functions . 2. n = 0, 1 figure 8-11. interval ti mer operation timing (1/2) (a) basic operation t count clock tm5n count value cr5n tce5n inttm5n count start clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time remark interval time = (n + 1) t n = 01h to ffh n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 254 figure 8-11. interval ti mer operation timing (2/2) (b) when cr5n = 00h t interval time count clock tm5n cr5n tce5n inttm5n 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 255 8.4.2 operation as external event counter the external event counter c ounts the number of external clock pulses to be input to the ti5n pin by 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock selection regist er 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit ti mer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the va lue of cr5n, inttm5n is generated. setting <1> set each register. ? set the port mode register (pm17 or pm33) note to 1. ? tcl5n: select ti5n pin input edge. ti5n pin falling edge tcl5n = 00h ti5n pin rising edge tcl5n = 01h ? cr5n: compare value ? tmc5n: stop the count operation, select the mode in which clear & start occurs on match of tm5n and cr5n, disable the timer f/f inversion operation, disable timer output. (tmc5n = 0000 00b = don?t care) <2> when tce5n = 1 is set, the number of pu lses input from the ti5n pin is counted. <3> when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> after these settings, inttm5n is generated each time the values of tm5n and cr5n match. note 8-bit timer/event counter 50: pm17 8-bit timer/event counter 51: pm33 remark for how to enable the inttm5n signal interrupt, see chapter 19 interrupt functions . figure 8-12. external event counter oper ation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n count start remark n = 00h to ffh n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 256 8.4.3 square-wave output operation a square wave with any selected frequency is output at in tervals determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is inverted at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control r egister 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. ? clear the port output latch (p17 or p33) note and port mode register (pm17 or pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operat ion, select the mode in which clear & start occurs on a match of tm5n and cr5n. lvs5n lvr5n timer output f/f status setting 1 0 timer output f/f clear (0) (default output value of to50 pin: low level) 0 1 timer output f/f set (1) (default ou tput value of to5n pin: high level) timer output enabled (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> the timer output f/f is inverted by a match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> after these settings, the timer output f/f is inverted at the same interval and a square wave is output from to5n. the frequency is as follows. ? frequency = 1/2t (n + 1) (n: 00h to ffh) note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 caution do not write other values to cr5n during operation. remarks 1. for how to enable the inttm5n signal interrupt, see chapter 19 interrupt functions . 2. n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 257 figure 8-13. square-wave output operation timing count clock tm5n count value 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h cr5n to5n note t count start note the initial value of to5n output c an be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). 8.4.4 pwm output operation 8-bit timer/event counter 5n operates as a pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty pulse determined by the value set to 8-bit time r compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n; the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled with bit 0 (toe5n) of tmc5n. caution in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 258 (1) pwm output basic operation setting <1> set each register. ? clear the port output latch (p17 or p33) note and port mode register (pm17 or pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select pwm mode. the timer output f/f is not changed. tmc5n1 active level selection 0 active-high 1 active-low timer output enabled (tmc5n = 01000001b or 01000011b) <2> the count operation starts when tce5n = 1. clear tce5n to 0 to stop the count operation. note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 pwm output operation <1> pwm output (output from to5n) outputs an inactive level until an overflow occurs. <2> when an overflow occurs, the active level is output. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after the cr5n matches the count value, the inacti ve level is output until an overflow occurs again. <4> operations <2> and <3> are repe ated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output becomes inactive. for details of timing, see figures 8-14 and 8-15 . the cycle, active-level width, and duty are as follows. ? cycle = 2 8 t ? active-level width = nt ? duty = n/2 8 (n = 00h to ffh) remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 259 figure 8-14. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n <2> active level <1> inactive level <3> inactive level <5> inactive level t <2> active level (b) cr5n = 00h count clock tm5n cr5n tce5n inttm5n 01h 00h ffh 00h 01h 02h 00h ffh 00h 01h 02h m 00h to5n l (inactive level) t (c) cr5n = ffh tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h ffh <1> inactive level <2> active level ffh 00h 01h 02h m 00h <3> inactive level <2> active level <5> inactive level t remarks 1. <1> to <3> and <5> in figure 8-14 (a) correspond to <1> to <3> and <5> in pwm output operation in 8.4.4 (1) pwm output basic operation . 2. n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 260 (2) operation with cr5n changed figure 8-15. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh value is transferred to cr5n at overflow immediately after change. count clock tm5n cr5n tce5n inttm5n to5n <1> cr5n change (n m) n n + 1 n + 2 ffh 00h 01h m m + 1 m + 2 ffh 00h 01h 02h m m + 1 m + 2 n 02h m h <2> t (b) cr5n value is changed from n to m after clock rising edge of ffh value is transferred to cr5n at second overflow. count clock tm5n cr5n tce5n inttm5n to5n n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h m m m + 1 m + 2 <1> cr5n change (n m) <2> t caution when reading from cr5n betw een <1> and <2> in figure 8-15, the value read differs from the actual value (read value: m, actual value of cr5n: n).
chapter 8 8-bit timer/event counters 50 and 51 preliminary user?s manual u17260ej3v1ud 261 8.5 cautions for 8-bit ti mer/event counters 50 and 51 (1) timer start error an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 8-bit timer counters 50 and 51 (tm50, tm 51) are started asynchronous ly to the count clock. figure 8-16. 8-bit timer counter 5n start timing count clock tm5n count value 00h 01h 02h 03h 04h timer start remark n = 0, 1
preliminary user?s manual u17260ej3v1ud 262 chapter 9 8-bit timers h0 and h1 9.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 have the following functions. ? interval timer ? square-wave output ? pwm output ? carrier generator (8-bit timer h1 only) 9.2 configuration of 8-bit timers h0 and h1 8-bit timers h0 and h1 include the following hardware. table 9-1. configuration of 8-bit timers h0 and h1 item configuration timer register 8-bit timer counter hn registers 8-bit timer h compare register 0n (cmp0n) 8-bit timer h compare register 1n (cmp1n) timer output tohn, output controller control registers 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register 1 (tmcyc1) note port mode register 1 (pm1) port register 1 (p1) note 8-bit timer h1 only remark n = 0, 1 figures 9-1 and 9-2 show the block diagrams.
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 263 figure 9-1. block diag ram of 8-bit timer h0 tmhe0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 toh0/p15 inttmh0 f prs f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 1 0 f/f r 3 2 pm15 match internal bus 8-bit timer h mode register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder selector interrupt generator output controller level inversion pwm mode signal timer h enable signal clear 8-bit timer h compare register 00 (cmp00) output latch (p15) 8-bit timer/ event counter 50 output selector 8-bit timer counter h0
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 264 figure 9-2. block diag ram of 8-bit timer h1 match internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h compare register 1 1 (cmp11) decoder toh1/ intp5/ p16 8-bit timer h carrier control register 1 (tmcyc1) inttmh1 inttm51 selector f prs f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl f rl /2 7 f rl /2 9 interrupt generator output controller level inversion pm16 output latch (p16) 1 0 f/f r pwm mode signal carrier generator mode signal timer h enable signal 3 2 8-bit timer h compare register 0 1 (cmp01) 8-bit timer counter h1 clear rmc1 nrzb1 nrz1 reload/ interrupt control 8-bit timer h mode register 1 (tmhmd1) selector
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 265 (1) 8-bit timer h compar e register 0n (cmp0n) this register can be read or written by an 8-bit memory mani pulation instruction. this r egister is used in all of the timer operation modes. this register constantly compares t he value set to cmp0n with the count val ue of the 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttm hn) and inverts the output level of tohn. rewrite the value of cmp0n while the timer is stopped (tmhen = 0). a reset signal generation sets this register to 00h. figure 9-3. format of 8-bit time r h compare register 0n (cmp0n) symbol cmp0n (n = 0, 1) address: ff18h (cmp00), ff1ah (cmp01) after reset: 00h r/w 7 6 5 4 32 1 0 (2) 8-bit timer h compar e register 1n (cmp1n) this register can be read or written by an 8-bit memory manipulation instruction. this register is used in the pwm output mode and carrier generator mode. in the pwm output mode, this register constantly compares the value set to cmp1n with the count value of the 8- bit timer counter hn and, when the two values match, in verts the output level of tohn. no interrupt request signal is generated. in the carrier generator mode, the cm p1n register always compares the val ue set to cmp1n with the count value of the 8-bit timer counter hn and, wh en the two values match, generates an in terrupt request signal (inttmhn). at the same time, the count value is cleared. cmp1n can be rewritten during timer count operation. if the value of cmp1n is rewritten while the timer is oper ating, the new value is la tched and transferred to cmp1n when the count value of the timer matches the old val ue of cmp1n, and then the valu e of cmp1n is changed to the new value. if matching of the count value and the cmp1n value and wr iting a value to cmp1n conflict, the value of cmp1n is not changed. a reset signal generation sets this register to 00h. figure 9-4. format of 8-bit time r h compare register 1n (cmp1n) symbol cmp1n (n = 0, 1) address: ff19h (cmp10), ff1bh (cmp11) after reset: 00h r/w 7 6 5 4 32 1 0 caution in the pwm output mode and carrier genera tor mode, be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the ti mer count operation was stopped (tmhen = 0) (be sure to set again even if se tting the same value to cmp1n). remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 266 9.3 registers controlling 8-bit timers h0 and h1 the following four registers are used to control 8-bit timers h0 and h1. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register 1 (tmcyc1) note ? port mode register 1 (pm1) ? port register 1 (p1) note 8-bit timer h1 only (1) 8-bit timer h mode register n (tmhmdn) this register controls the mode of timer h. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 267 figure 9-5. format of 8-bit time r h mode register 0 (tmhmd0) tmhe0 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe0 0 1 timer operation enable tmhmd0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w f prs f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 tm50 output note setting prohibited cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 f prs = 2 mhz 2 mhz 1 mhz 500 khz 31.25 khz 1.95 khz count clock selection other than above interval timer mode pwm output mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> f prs = 5 mhz 5 mhz 2.5 mhz 1.25 mhz 78.13 khz 4.88 khz f prs = 10 mhz 10 mhz 5 mhz 2.5 mhz 156.25 khz 9.77 khz f prs = 20 mhz 20 mhz 10 mhz 5 mhz 312.5 khz 19.54 khz note note the following points when select ing the tm50 output as the count clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of the 8-bit timer/event counter 50 first and t hen enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of the 8-bit time r/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable the to50 pin as a timer output pin in any mode.
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 268 cautions 1. when tmhe0 = 1, setting th e other bits of tmhmd0 is prohibited. 2. in the pwm output mode, be sure to set the 8-bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to cmp10). remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 269 figure 9-6. format of 8-bit time r h mode register 1 (tmhmd1) tmhe1 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control <7> 6 5 4 3 2 <1> <0> f prs f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl /2 7 f rl /2 9 f rl cks12 0 0 0 0 1 1 1 1 cks11 0 0 1 1 0 0 1 1 cks10 0 1 0 1 0 1 0 1 f prs = 2 mhz 2 mhz 500 khz 125 khz 31.25 khz 0.49 khz 1.88 khz (typ.) 0.47 khz (typ.) 240 khz (typ.) count clock selection f prs = 5 mhz 5 mhz 1.25 mhz 312.5 khz 78.13 khz 1.22 khz f prs = 10 mhz 10 mhz 2.5 mhz 625 khz 156.25 khz 2.44 khz f prs = 20 mhz 20 mhz 5 mhz 1.25 mhz 312.5 khz 4.88 khz cautions 1. when tmhe1 = 1, setting th e other bits of tmhmd1 is prohibited. 2. in the pwm output mode and carrier generato r mode, be sure to set the 8-bit timer h compare register 11 (cmp11) when star ting the timer count operation (tmh e1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to cmp11). 3. when the carrier generator mode is used, set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. remarks 1. f prs : peripheral hardware clock frequency 2. f rl : internal low-speed oscillation clock frequency
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 270 (2) 8-bit timer h carrier control register 1 (tmcyc1) this register controls the remote control output and carrier pulse output status of 8-bit timer h1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 9-7. format of 8-bit timer h carrier control register 1 (tmcyc1) 0 tmcyc1 0 0 0 0 rmc1 nrzb1 nrz1 address: ff6dh after reset: 00h r/w note low-level output high-level output low-level output carrier pulse output rmc1 0 0 1 1 nrzb1 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enabled status (rmc1 = 1: carrier pulse output, rmc1 = 0: high-level status) nrz1 0 1 carrier pulse output status flag <0> note bit 0 is read-only. (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p15/toh0 and p16/toh1/intp5 pins for timer output, clear pm15 and pm16 and the output latches of p15 and p16 to 0. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 9-8. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 271 9.4 operation of 8-bit timers h0 and h1 9.4.1 operation as inter val timer/square-wave output when the 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and the 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval timer mode. since a match of the 8-bit timer counter hn and the cmp1n register is not detect ed even if the cmp1n register is set, timer output is not affected. by setting bit 0 (toenn) of timer h mode register n (tmh mdn) to 1, a square wave of any frequency (duty = 50%) is output from tohn. setting <1> set each register. figure 9-9. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting default setting of timer output level interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting the interval time is as follows if n is set as a comparison value. ? interval time = (n +1)/f cnt <2> count operation starts when tmhen = 1. <3> when the values of the 8-bit timer counter hn and the cmp0n register match, the inttmhn signal is generated and the 8-bit timer counter hn is cleared to 00h. <4> subsequently, the inttmhn signal is generated at t he same interval. to stop the count operation, clear tmhen to 0. remarks 1. for the setting of the output pin, see 9.3 (3) port mode register 1 (pm1) . 2. for how to enable the inttmhn signal interrupt, see chapter 19 interrupt functions . 3. n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 272 figure 9-10. timing of interval time r/square-wave output operation (1/2) (a) basic operation (operation when 01h cmp0n feh) 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the value of the 8-bit timer counter hn matches the value of the cmp0n regist er, the value of the timer counter is cleared, and the level of th e tohn output is inverted. in addition, the inttmhn signal is output at the rising edge of the count clock. <3> if the tmhen bit is cleared to 0 while timer h is oper ating, the inttmhn signal and tohn output are set to the default level. if they are already at the default level before the tmhen bit is cleared to 0, then that level is maintained. remark n = 0, 1 01h n feh
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 273 figure 9-10. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 00h 00h interval time remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 274 9.4.2 operation as pwm output in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. the 8-bit timer compare register 0n (cmp0n) controls the cycle of timer output (tohn). rewriting the cmp0n register during timer operation is prohibited. the 8-bit timer compare register 1n (cmp1n) controls the duty of timer output (toh n). rewriting the cmp1n register during timer operation is possible. the operation in pwm output mode is as follows. the tohn output level is inverted and t he 8-bit timer counter hn is cleared to 0 when the 8-bit timer counter hn and the cmp0n register match after the time r count is started. the tohn output level is inverted when the 8-bit timer counter hn and the cmp1n register match. setting <1> set each register. figure 9-11. register setting in pwm output mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled default setting of timer output level pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0, 1 2. 00h cmp1n (m) < cmp0n (n) ffh <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare re gister that is to be compared first after counter operation is enabled. when the values of the 8-bit timer c ounter hn and the cmp0n register matc h, the 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, and tohn output is inverted. at the same time, the compare register to be compared with the 8-bit time r counter hn is changed from the cmp0n register to the cmp1n register. <4> when the 8-bit timer counter hn and the cmp1n regi ster match, tohn output is inverted and the compare register to be compared with the 8- bit timer counter hn is changed from the cmp1n register to the cmp0n register. at this time, the 8-bit timer counter hn is not cleared and the inttmhn signal is not generated.
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 275 <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n regist er is n, the setting value of the cmp1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. ? pwm pulse output cycle = (n + 1)/f cnt ? duty = (m + 1)/(n + 1) cautions 1. the set value of the cmp1n register ca n be changed while the time r counter is operating. however, this takes a duration of three operati ng clocks (signal selected by the cksn2 to cksn0 bits of the tmhmdn register) from when the value of the cmp1n register is changed until the value is transferred to the register. 2. be sure to set the cmp1n register when st arting the timer count opera tion (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). 3. make sure that the cmp1n re gister setting value (m) and cmp0 n register setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) ffh remarks 1. for the setting of the output pin, see 9.3 (3) port mode register 1 (pm1) . 2. for details on how to enable the inttmhn signal interrupt, see chapter 19 interrupt functions . 3. n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 276 figure 9-12. operation timing in pwm output mode (1/4) (a) basic operation count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp1n a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhen bit to 1. start the 8-bit timer counter hn by masking one count clock to count up. at this time, tohn output remains the default. <2> when the values of the 8-bit timer counter hn and the cmp0n register match, the tohn output level is inverted, the value of the 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the values of the 8-bit timer counter hn and the cmp1n register match, the tohn output level is inverted. at this time, the 8-bit timer counter val ue is not cleared and the inttmhn signal is not output. <4> clearing the tmhen bit to 0 during timer hn operat ion sets the inttmhn signal and tohn output to the default. remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 277 figure 9-12. operation timing in pwm output mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 278 figure 9-12. operation timing in pwm output mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 279 figure 9-12. operation timing in pwm output mode (4/4) (e) operation by changi ng cmp1n (cmp1n = 02h 03h, cmp0n = a5h) count clock 8-bit timer counter hn cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h <1> <4> <3> <2> cmp11 <6> <5> 02h a5h 03h 02h (03h) <2>? 80h <1> the count operation is enabled by setting tmhen = 1. start the 8-bit timer counter hn by masking one count clock to count up. at this time , the tohn output remains default. <2> the cmp1n register value can be changed during timer counter operation. this operation is asynchronous to the count clock. <3> when the values of the 8-bit timer counter hn and t he cmp0n register match, t he value of the 8-bit timer counter hn is cleared, the tohn output level is inverted, and the inttmhn signal is output. <4> if the cmp1n register value is changed, the value is latched and not transferred to the register. when the values of the 8-bit timer counter hn and the cmp1 n register before the cha nge match, the value is transferred to the cmp1n register and the cm p1n register value is changed (<2>?). however, three count clocks or more are required fr om when the cmp1n register value is changed to when the value is transferred to the register. if a match signal is generated within thr ee count clocks, the changed value cannot be transferred to the register. <5> when the values of the 8-bit timer counter hn and the cmp1n register after t he change match, the tohn output level is inverted. the 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <6> clearing the tmhen bit to 0 during timer hn operati on makes the inttmhn signal and tohn output default. remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 280 9.4.3 carrier generator opera tion (8-bit timer h1 only) in the carrier generator mode, the 8-bit timer h1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). the carrier clock generated by the 8-bit timer h1 is output in the cycle set by the 8-bit timer/event counter 51. in carrier generator mode, the output of the 8-bit timer h1 carrier pulse is controlled by the 8-bit timer/event counter 51, and the carrier pulse is output from the toh1 output. (1) carrier generation in carrier generator mode, the 8-bit timer h compare r egister 01 (cmp01) generates a low-level width carrier pulse waveform and the 8-bit timer h compare register 11 (cmp11) generates a high-level width carrier pulse waveform. rewriting the cmp11 register during t he 8-bit timer h1 operation is possible but rewriting the cm p01 register is prohibited. (2) carrier output control carrier output is controlled by the in terrupt request signal (inttm51) of t he 8-bit timer/event counter 51 and the nrzb1 and rmc1 bits of the 8-bit timer h carrier co ntrol register (tmcyc1). the relationship between the outputs is shown below. rmc1 bit nrzb1 bit output 0 0 low-level output 0 1 high-level output 1 0 low-level output 1 1 carrier pulse output
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 281 to control the carrier pulse output during a count operation, the nrz1 and nrzb1 bits of the tmcyc1 register have a master and slave bit configuratio n. the nrz1 bit is read-only but t he nrzb1 bit can be read and written. the inttm51 signal is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal of the nrz1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the timing for transfer from the nrz b1 bit to the nrz1 bit is as shown below. figure 9-13. transfer timing 8-bit timer h1 count clock tmhe1 inttm51 inttm5h1 nrz1 nrzb1 rmc1 1 1 1 0 00 <1> <2> <3> <1> the inttm51 signal is synchronized with the count clock of the 8-bit timer h1 and is output as the inttm5h1 signal. <2> the value of the nrzb1 bit is tr ansferred to the nrz1 bit at the second clock from the rising edge of the inttm5h1 signal. <3> write the next value to the nrzb1 bit in the inte rrupt servicing program t hat has been started by the inttm5h1 interrupt or after timing has been checked by polling the interrupt request flag. write data to count the next time to the cr51 register. cautions 1. do not rewrite the nrzb1 bit again until at least the second clock afte r it has been rewritten, or else the transfer from the nrzb1 bi t to the nrz1 bit is not guaranteed. 2. when the 8-bit timer/event c ounter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. when the 8-bit time r/event counter 51 is used in a mode other than the carrier generator mode, the timi ng of the interrupt generation differs.
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 282 setting <1> set each register. figure 9-14. register setting in carrier generator mode (i) setting 8-bit timer h m ode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 timer output enabled default setting of timer output level carrier generator mode selection count clock (f cnt ) selection count operation stopped 1 0/1 1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 (ii) cmp01 register setting ? compare value (iii) cmp11 register setting ? compare value (iv) tmcyc1 register setting ? rmc1 = 1 ... remote control output enable bit ? nrzb1 = 0/1 ... carrier output enable bit (v) tcl51 and tmc51 register setting ? see 8.3 registers controlling 8-bit timer/event counters 50 and 51 . <2> when tmhe1 = 1, the 8-bit timer h1 starts counting. <3> when tce51 of the 8-bit timer mode control register 51 (tmc51) is set to 1, the 8-bit timer/event counter 51 starts counting. <4> after the count operation is enabled, the first compar e register to be compared is the cmp01 register. when the count value of the 8-bit timer counter h1 and the cmp01 register value match, the inttmh1 signal is generated, the 8-bit timer c ounter h1 is cleared. at the same time, the compare register to be compared with the 8-bit timer counter h1 is switc hed from the cmp01 register to the cmp11 register. <5> when the count value of the 8-bit timer counter h1 and the cmp11 register value match, the inttmh1 signal is generated, the 8-bit timer c ounter h1 is cleared. at the same time, the compare register to be compared with the 8-bit timer counter h1 is switc hed from the cmp11 register to the cmp01 register. <6> by performing procedures <4> and <5> r epeatedly, a carrier clock is generated. <7> the inttm51 signal is synchronized with count clock of the 8-bit timer h1 and output as the inttm5h1 signal. the inttm5h1 signal becomes the data trans fer signal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <8> write the next value to the nrzb1 bit in the inte rrupt servicing program that has been started by the inttm5h1 interrupt or after timing has been checked by polling the interrupt request flag. write data to count the next time to the cr51 register. <9> when the nrz1 bit is high level, a carri er clock is output from the toh1 pin.
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 283 <10> by performing the procedures above, an arbitrary carrier clock is obtained. to stop the count operation, clear tmhe1 to 0. if the setting value of the cmp01 regist er is n, the setting value of the cmp11 register is m, and the count clock frequency is f cnt , the carrier clock output cycle and duty are as follows. ? carrier clock output cycle = (n + m + 2)/f cnt ? duty = high-level width/carrier cl ock output width = (m + 1)/(n + m + 2) cautions 1. be sure to set the cmp11 register when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmh e1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 2. set so that the count clock frequency of tmh1 becomes more th an 6 times the count clock frequency of tm51. 3. set the values of the cmp01 and cmp 11 registers in a range of 01h to ffh. 4. the set value of the cmp11 register can be changed while the timer counter is operating. however, it takes the duration of three operating clocks (signal selected by the cks12 to cks10 bits of the tmhmd1 re gister) since the val ue of the cmp11 register has been changed until the val ue is transferred to the register. 5. be sure to set the rmc1 bit be fore the count operation is started. remarks 1. for the setting of the output pin, see 9.3 (3) port mode register 1 (pm1) . 2. for how to enable the inttmh1 signal interrupt, see chapter 19 interrupt functions .
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 284 figure 9-15. carrier generator mode operation timing (1/3) (a) operation when cmp01 = n, cmp11 = n cmp01 cmp11 tmhe11 inttmh1 carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 51 count clock tm51 count value cr5 1 tce5 1 toh 11 0 0 1 1 0 0 1 1 0 0 inttm5n 1 nrzb 1 nrz 1 carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5h 1 <1><2> <3> <4> <5> <6> <7> 8-bit timer h1 count clock 8-bit timer counter h1 count value k l m n <1> when tmhe1 = 0 and tce51 = 0, the 8-bi t timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, the 8-bit timer counter h1 starts a count operation. at that time, the carrier clock remains default. <3> when the count value of the 8-bit timer counter h1 matches the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8- bit timer counter h1 is switched from the cmp01 register to the cmp11 r egister. the 8-bit timer counter h1 is cleared to 00h. <4> when the count value of the 8-bit timer counter h1 matches the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. the 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. <6> the inttm5h1 signal becomes the data transfer si gnal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <7> when nrz1 = 0 is set, the toh1 output becomes low level.
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 285 figure 9-15. carrier generator mode operation timing (2/3) (b) operation when cmp01 = n, cmp11 = m n cmp01 cmp11 tmhe1 inttmh1 carrier clock tm51 count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m tce51 toh1 0 0 1 1 0 0 1 1 0 0 inttm51 nrzb1 nrz1 carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5h1 <1><2> <3> <4> <5> <6> <7> 8-bit timer 51 count clock 8-bit timer h1 count clock 8-bit timer counter h1 count value k cr51 l m n <1> when tmhe1 = 0 and tce51 = 0, the 8-bi t timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, the 8-bit timer counter h1 starts a count operation. at that time, the carrier clock remains default. <3> when the count value of the 8-bit timer counter h1 matches the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8- bit timer counter h1 is switched from the cmp01 register to the cmp11 r egister. the 8-bit timer counter h1 is cleared to 00h. <4> when the count value of the 8-bit timer counter h1 matches the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. the 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly , a carrier clock with duty fixed to other than 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. <6> a carrier signal is output at the first rising edge of the carrier clock if nrz1 is set to 1. <7> when nrz1 = 0, the toh1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u17260ej3v1ud 286 figure 9-15. carrier generator mode operation timing (3/3) (c) operation when cmp11 is changed 8-bit timer h1 count clock cmp01 tmhe1 inttmh1 carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>? <4> <3> <2> cmp11 <5> m n l m (l) 8-bit timer counter h1 count value <1> when tmhe1 = 1 is set, the 8-bit timer h1 starts a c ount operation. at that time, the carrier clock remains default. <2> when the count value of the 8-bit timer counter h1 matches the value of the cmp01 register, the inttmh1 signal is output, the carrier signal is inverted, and the ti mer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with t hat of the 8-bit timer count er h1 is changed from the cmp01 register to the cmp11 register. <3> the cmp11 register is asynchronous to the count cl ock, and its value can be changed while the 8-bit timer h1 is operating. the new value (l) to which the value of the register is to be changed is latched. when the count value of the 8-bit timer counter h1 matches the value (m) of the cmp11 regist er before the change, the cmp11 register is changed (<3>?). however, it takes three count clo cks or more since the value of the cmp11 register ha s been changed until the value is transferred to the regist er. even if a match signal is generat ed before the duration of three count clocks elapses, the new value is not transferred to the register. <4> when the count value of 8-bit timer counter h1 ma tches the value (m) of the cmp1 register before the change, the inttmh1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with that of the 8-bit timer counter h1 is changed from the cmp11 regi ster to the cmp01 register. <5> the timing at which the count value of the 8-bit ti mer counter h1 and the cmp11 register value match again is indicated by the value after the change (l).
preliminary user?s manual u17260ej3v1ud 287 chapter 10 watch timer 10.1 functions of watch timer the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. figure 10-1 shows the watch timer block diagram. figure 10-1. block diagram of watch timer f prs /2 7 f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f sub intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 f w clear 11-bit prescaler clear 5-bit counter watch timer operation mode register (wtm) internal bus selector selector selector selector f wx /2 4 f wx /2 5 f wx remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) f wx : f w or f w /2 9
chapter 10 watch timer preliminary user?s manual u17260ej3v1ud 288 (1) watch timer when the peripheral hardware clock or subsystem cloc k is used, interrupt request signals (intwt) are generated at preset intervals. table 10-1. watch timer interrupt time interrupt time when operated at f sub = 32.768 khz when operated at f prs = 2 mhz when operated at f prs = 5 mhz when operated at f prs = 10 mhz when operated at f prs = 20 mhz 2 4 /f w 488 s 1.02 ms 410 s 205 s 102 s 2 5 /f w 977 s 2.05 ms 819 s 410 s 205 s 2 13 /f w 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms 2 14 /f w 0.5 s 1.05 s 0.419 s 0. 210 s 0.105 s remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) (2) interval timer interrupt request signals (intwti) are generated at preset time intervals. table 10-2. interval timer interval time interval time when operated at f sub = 32.768 khz when operated at f prs = 2 mhz when operated at f prs = 5 mhz when operated at f prs = 10 mhz when operated at f prs = 20 mhz 2 4 /f w 488 s 1.02 ms 410 s 205 s 102 s 2 5 /f w 977 s 2.05 ms 820 s 410 s 205 s 2 6 /f w 1.95 ms 4.10 ms 1.64 ms 820 s 410 s 2 7 /f w 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820 s 2 8 /f w 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms 2 9 /f w 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms 2 10 /f w 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms 2 11 /f w 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) 10.2 configuration of watch timer the watch timer includes the following hardware. table 10-3. watch timer configuration item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm)
chapter 10 watch timer preliminary user?s manual u17260ej3v1ud 289 10.3 register controlling watch timer the watch timer is controlled by the wa tch timer operation mode register (wtm). ? watch timer operation mode register (wtm) this register sets the watch timer count clock, enabl es/disables operation, prescaler interval time, and 5-bit counter operation control. wtm is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets wtm to 00h. figure 10-2. format of watch timer operation mode register (wtm) address: ff6fh after reset: 00h r/w symbol 7 6 5 4 3 2 <1> <0> wtm wtm7 wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 watch timer count clock selection (f w ) wtm7 f sub = 32.768 khz f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 f prs /2 7 ? 15.625 khz 39.062 khz 78.125 khz 156.25 khz 1 f sub 32.768 khz ? wtm6 wtm5 wtm4 prescaler interval time selection 0 0 0 2 4 /f w 0 0 1 2 5 /f w 0 1 0 2 6 /f w 0 1 1 2 7 /f w 1 0 0 2 8 /f w 1 0 1 2 9 /f w 1 1 0 2 10 /f w 1 1 1 2 11 /f w wtm3 wtm2 selection of watch timer interrupt time 0 0 2 14 /f w 0 1 2 13 /f w 1 0 2 5 /f w 1 1 2 4 /f w wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation enable 0 operation stop (clear bot h prescaler and 5-bit counter) 1 operation enable
chapter 10 watch timer preliminary user?s manual u17260ej3v1ud 290 caution do not change the count clock and interval ti me (by setting bits 4 to 7 (wtm4 to wtm7) of wtm) during watch timer operation. remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency
chapter 10 watch timer preliminary user?s manual u17260ej3v1ud 291 10.4 watch timer operations 10.4.1 watch timer operation the watch timer generates an interrupt request signal (int wt) at a specific time interval by using the peripheral hardware clock or subsystem clock. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer oper ation mode register (wtm) are set to 1, the count operation starts. when these bits are cleared to 0, t he 5-bit counter is cleared an d the count operation stops. when the interval timer is simultaneously operated, zero -second start can be achieved only for the watch timer by clearing wtm1 to 0. in this case, however, the 11-bit prescaler is not cleared. therefore, an error up to 2 9 1/f w seconds occurs in the first overfl ow (intwt) after zero-second start. the interrupt request is generated at the following time intervals. table 10-4. watch timer interrupt time wtm3 wtm2 interrupt time selection when operated at f sub = 32.768 khz (wtm7 = 1) when operated at f prs = 2 mhz (wtm7 = 0) when operated at f prs = 5 mhz (wtm7 = 0) when operated at f prs = 10 mhz (wtm7 = 0) when operated at f prs = 20 mhz (wtm7 = 0) 0 0 2 14 /f w 0.5 s 1.05 s 0.419 s 0. 210 s 0.105 s 0 1 2 13 /f w 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms 1 0 2 5 /f w 977 s 2.05 ms 819 s 410 s 205 s 1 1 2 4 /f w 488 s 1.02 ms 410 s 205 s 102 s remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency 10.4.2 interval timer operation the watch timer operates as interval timer which gener ates interrupt request signal s (intwti) repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm 4 to wtm6) of the watch timer operation mode register (wtm). when bit 0 (wtm0) of the wtm is set to 1, the count operation starts. when this bit is set to 0, the count operation stops. table 10-5. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at f sub = 32.768 khz (wtm7 = 1) when operated at f prs = 2 mhz (wtm7 = 0) when operated at f prs = 5 mhz (wtm7 = 0) when operated at f prs = 10 mhz (wtm7 = 0) when operated at f prs = 20 mhz (wtm7 = 0) 0 0 0 2 4 /f w 488 s 1.02 ms 410 s 205 s 102 s 0 0 1 2 5 /f w 977 s 2.05 ms 820 s 410 s 205 s 0 1 0 2 6 /f w 1.95 ms 4.10 ms 1.64 ms 820 s 410 s 0 1 1 2 7 /f w 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820 s 1 0 0 2 8 /f w 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms 1 0 1 2 9 /f w 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms 1 1 0 2 10 /f w 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms 1 1 1 2 11 /f w 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency
chapter 10 watch timer preliminary user?s manual u17260ej3v1ud 292 figure 10-3. operation timing of watch timer/interval timer 0h start overflow overflow 5-bit counter count clock watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5 s) interval time (t) t interrupt time of watch timer (0.5 s) remark f w : watch timer clock frequency figures in parentheses are for operation with f w = 32.768 khz (wtm7 = 1, wtm3, wtm2 = 0, 0) 10.5 cautions for watch timer when operation of the watch timer and 5- bit counter is enabled by the watch timer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the in terval until the first interrupt request signal (intwt) is generated after the register is set does not exactly match th e specification made with bits 2 and 3 (wtm2, wtm3) of wtm. subsequently, however, the intwt signal is generated at the specified intervals. figure 10-4. example of generation of watc h timer interrupt request signal (intwt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 s longer). intwt is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt
preliminary user?s manual u17260ej3v1ud 293 chapter 11 watchdog timer 11.1 functions of watchdog timer the watchdog timer operates on the internal low-speed oscillation clock. the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. program loop is detected in the following cases. ? if the watchdog timer counter overflows ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if data is written to wdte during a window close period ? if the instruction is fetched from an area not set by the ims and ixs registers (detection of an invalid check while the cpu hangs up) ? if the cpu accesses an area that is not set by t he ims and ixs registers (excluding fb00h to ffffh) by executing a read/write instruct ion (detection of an abnormal access during a cpu program loop) when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 22 reset function .
chapter 11 watchdog timer preliminary user?s manual u17260ej3v1ud 294 11.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 11-1. configuration of watchdog timer item configuration control register watchdog timer enable register (wdte) how the counter operation is controlled, overflow ti me, and window open period are set by the option byte. table 11-2. setting of op tion bytes and watchdog timer setting of watchdog timer option byte (0080h) window open period bits 6 and 5 (window1, window0) controlling counter operation of watchdog timer bit 4 (wdton) overflow time of watchdog timer bits 3 to 1 (wdcs2 to wdcs0) remark for the option byte, see chapter 25 option byte . figure 11-1. block diag ram of watchdog timer f rl /2 clock input controller reset output controller internal reset signal internal bus selector 17-bit counter 2 10 /f rl to 2 17 /f rl watchdog timer enable register (wdte) clear, reset control wdton of option byte (0080h) window1 and window0 of option byte (0080h) count clear signal wdcs2 to wdcs0 of option byte (0080h) overflow signal cpu access signal cpu access error detector window size determination signal
chapter 11 watchdog timer preliminary user?s manual u17260ej3v1ud 295 11.3 register controlling watchdog timer the watchdog timer is controlled by the watchdog timer enable register (wdte). (1) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 9ah or 1ah note . figure 11-2. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff99h after reset: 9ah/1ah note r/w note the wdte reset value differs depending on the wdto n setting value of the option byte (0080h). to operate watchdog timer, set wdton to 1. wdton setting value wdte reset value 0 (watchdog timer count operation disabled) 1ah 1 (watchdog timer count operation enabled) 9ah cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. if a 1-bit memory manipulation instructio n is executed for wdte, an internal reset signal is generated. if the source clock to the wa tchdog timer is stopped, however, an internal reset signal is genera ted when the source clock to th e watchdog timer resumes operation. 3. the value read from wdte is 9ah/1ah (this differs fr om the written value (ach)).
chapter 11 watchdog timer preliminary user?s manual u17260ej3v1ud 296 11.4 operation of watchdog timer 11.4.1 controlling operation of watchdog timer 1. when the watchdog timer is used, its operati on is specified by the option byte (0080h). ? enable counting operation of the watchdog timer by se tting bit 4 (wdton) of the option byte (0080h) to 1 (the counter starts operating after a reset release) (for details, see chapter 25 ). wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped after rese t), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled ? set an overflow time by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h) (for details, see 11.4.2 and chapter 25 ). ? set a window open period by using bits 6 and 5 (wi ndow1 and window0) of the opt ion byte (0080h) (for details, see 11.4.3 and chapter 25 ). 2. after a reset release, the watchdog timer starts counting. 3. by writing ?ach? to wdte after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cl eared and starts counting again. 4. after that, write wdte the second time or later afte r a reset release during the window open period. if wdte is written during a window close period, an internal reset signal is generated. 5. if the overflow time expires without ?ach? wri tten to wdte, an internal reset signal is generated. a internal reset signal is generated in the following cases. ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if the instruction is fetched from an area not set by the ims and ixs registers (det ection of an invalid check during a cpu program loop) ? if the cpu accesses an area not set by the ims and ixs registers (excluding fb00h to ffffh) by executing a read/write instruction (det ection of an abnormal access during a cpu program loop) cautions 1. the first writing to wdte after a reset releas e clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. 2. if the watchdog timer is cleared by writi ng ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f rl seconds. 3. the watchdog timer can be cleared immediately before the count value overflows (ffffh).
chapter 11 watchdog timer preliminary user?s manual u17260ej3v1ud 297 cautions 4. the operation of the watchdog time r in the halt and stop modes differs as follows depending on the set value of bit 0 (lsrosc) of the option byte. lsrosc = 0 (internal low-speed oscillator can be stopped by software) lsrosc = 1 (internal low-speed oscillator cannot be stopped) in halt mode in stop mode watchdog timer operation stops. watchdog timer operation continues. if lsrosc = 0, the watchdog timer resu mes counting after the halt or stop mode is released. at this time, the counter is not clear ed to 0 but starts counting from the value at which it was stopped. if oscillation of the internal low-speed osc illator is stopped by setting lsrstop (bit 1 of the internal oscillation mode register (rcm) = 1) when lsrosc = 0, the watchdog timer stops operating. at this time, the counter is not cleared to 0. 5. the watchdog timer does not stop duri ng self-programming of th e flash memory and eeprom tm emulation. during processing, the interrupt acknowle dge time is delayed. set the overflow time and window size taki ng this delay into consideration. 11.4.2 setting overflow time of watchdog timer set the overflow time of the watchdog timer by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h). if an overflow occurs, an internal reset signal is generat ed. the present count is cleared and the watchdog timer starts counting again by writing ?ach? to wdte dur ing the window open period before the overflow time. the following overflow time is set. table 11-3. setting of over flow time of watchdog timer wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 0 0 0 2 10 /f rl (3.88 ms) 0 0 1 2 11 /f rl (7.76 ms) 0 1 0 2 12 /f rl (15.52 ms) 0 1 1 2 13 /f rl (31.03 ms) 1 0 0 2 14 /f rl (62.06 ms) 1 0 1 2 15 /f rl (124.12 ms) 1 1 0 2 16 /f rl (248.24 ms) 1 1 1 2 17 /f rl (496.48 ms) cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer does not stop duri ng self-programming of the flash memory and eeprom emulation. during processing, the interrupt ackno wledge time is delayed. set the overflow time and window size taking this delay into consideration. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 264 khz (max.)
chapter 11 watchdog timer preliminary user?s manual u17260ej3v1ud 298 11.4.3 setting window open period of watchdog timer set the window open period of the watchdog timer by usi ng bits 6 and 5 (window1, window0) of the option byte (0080h). the outline of the window is as follows. ? if ?ach? is written to wdte during the window open per iod, the watchdog timer is cleared and starts counting again. ? even if ?ach? is written to wdte during the window cl ose period, an abnormality is detected and an internal reset signal is generated. example : if the window open period is 25% window close period (75%) window open period (25%) counting starts overflow time counting starts again when ach is written to wdte. internal reset signal is generated if ach is written to wdte. caution the first writing to wdte after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of th e writing, and the watc hdog timer starts counting again. the window open period to be set is as follows. table 11-4. setting window open period of watchdog timer window1 window0 window open period of watchdog timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer does not stop durin g self-programming of the flash memory and eeprom emulation. during processing, the interrupt ackno wledge time is delayed. set the overflow time and window size taking this delay into consideration.
chapter 11 watchdog timer preliminary user?s manual u17260ej3v1ud 299 remark if the overflow time is set to 2 10 /f rl , the window close time and open time are as follows. setting of window open period 25% 50% 75% 100% window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms none window open time 3.56 to 3.88 ms 2.37 to 3.88 ms 0.119 to 3.88 ms 0 to 3.88 ms ? overflow time: 2 10 /f rl (max.) = 2 10 /264 khz (max.) = 3.88 ms ? window close time: 0 to 2 10 /f rl (min.) (1 ? 0.25) = 0 to 2 10 /216 khz (min.) 0.75 = 0 to 3.56 ms ? window open time: 2 10 /f rl (min.) (1 ? 0.25) to 2 10 /f rl (max.) = 2 10 /216 khz (min.) 0.75 to 2 10 /264 khz (max.) = 3.56 to 3.88 ms
preliminary user?s manual u17260ej3v1ud 300 chapter 12 clock output/buzzer output controller 12.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ics. the clock selected with t he clock output selection register (cks) is output. in addition, the buzzer output is intended for square- wave output of buzzer frequency selected with cks. figure 12-1 shows the block diagram of clock output/buzzer output controller. figure 12-1. block diagram of clo ck output/buzzer output controller f prs f prs /2 10 to f prs /2 13 f prs to f prs /2 7 f sub bzoe bcs1 bcs0 cloe cloe bzoe 84 pcl/intp6/p140 buz/intp7/p141 bcs0, bcs1 clock controller prescaler internal bus ccs3 clock output selection register (cks) ccs2 ccs1 ccs0 output latch (p141) pm141 output latch (p140) pm140 selector selector
chapter 12 clock output/buzzer output controller preliminary user?s manual u17260ej3v1ud 301 12.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller includes the following hardware. table 12-1. configuration of clock output/buzzer output controller item configuration control registers clock output selection register (cks) port mode register 14 (pm14) port register 14 (p14) 12.3 registers controlling clock output/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output selection register (cks) ? port mode register 14 (pm14) (1) clock output selection register (cks) this register sets output enable/disable for clock out put (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets cks to 00h.
chapter 12 clock output/buzzer output controller preliminary user?s manual u17260ej3v1ud 302 figure 12-2. format of clock out put selection register (cks) address: ff40h after reset: 00h r/w symbol <7> 6 5 <4> 3 2 1 0 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 clock division circui t operation stopped. buz fixed to low level. 1 clock division ci rcuit operation enabled. buz output enabled. buz output clock selection bcs1 bcs0 f prs = 10 mhz f prs = 20 mhz 0 0 f prs /2 10 9.77 khz 19.54 khz 0 1 f prs /2 11 4.88 khz 9.77 khz 1 0 f prs /2 12 2.44 khz 4.88 khz 1 1 f prs /2 13 1.22 khz 2.44 khz cloe pcl output enable/disable specification 0 clock division circui t operation stopped. pcl fixed to low level. 1 clock division ci rcuit operation enabled. pcl output enabled. pcl output clock selection ccs3 ccs2 ccs1 ccs0 f sub = 32.768 khz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs note 1 10 mhz setting prohibited note 2 0 0 0 1 f prs /2 5 mhz 10 mhz 0 0 1 0 f prs /2 2 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 312.5 khz 625 khz 0 1 1 0 f prs /2 6 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 ? 78.125 khz 156.25 khz 1 0 0 0 f sub 32.768 khz ? other than above setting prohibited notes 1. if the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 v v dd < 2.7 v, setting ccs3 = ccs2 = ccs1 = ccs0 = 0 (output clock of pcl: f prs ) is prohibited. 2. the pcl output clock prohibits settings if they exceed 10 mhz. cautions 1. set bcs1 and bcs0 when the bu zzer output operation is stopped (bzoe = 0). 2. set ccs3 to ccs0 while the clock output operation is stopped (cloe = 0). remarks 1. f prs : peripheral hardware clock frequency 2. f sub : subsystem clock frequency
chapter 12 clock output/buzzer output controller preliminary user?s manual u17260ej3v1ud 303 (2) port mode register 14 (pm14) this register sets port 14 input/output in 1-bit units. when using the p140/intp6/pcl pin for clock output and the p141/intp7/buz pin for buzzer output, clear pm140 and pm141 and the output latc hes of p140 and p141 to 0. pm14 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm14 to ffh. figure 12-3. format of port mode register 14 (pm14) address: ff2eh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm14 1 1 1 1 1 1 pm141 pm140 pm14n p14n pin i/o mode selection (n = 0, 1) 0 output mode (output buffer on) 1 input mode (output buffer off) 12.4 operations of clock output/buzzer output controller 12.4.1 operation as clock output the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output selection register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1 to enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. as show n in figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure) . when stopping output, do so after the high-level period of the clock. figure 12-4. remote control output application example cloe clock output ** 12.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (b cs0, bcs1) of the clock output selection register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output.
preliminary user?s manual u17260ej3v1ud 304 chapter 13 a/d converter 13.1 function of a/d converter the a/d converter converts an analog input signal into a digi tal value, and consists of up to eight channels (ani0 to ani7) with a resolution of 10 bits. the a/d converter has the following function. ? 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one analog input channel selected from ani0 to ani7. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. figure 13-1. block diag ram of a/d converter av ref av ss intad adcs bit adcs fr2 fr1 adce fr0 sample & hold circuit av ss voltage comparator a/d converter mode register (adm) internal bus 3 ads2 ads1 ads0 analog input channel specification register (ads) ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 controller a/d conversion result register (adcr) successive approximation register (sar) lv1 lv0 5 a/d port configuration register (adpc) adpc3 adpc2 adpc1 adpc0 4 selector tap selector
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 305 13.2 configuration of a/d converter the a/d converter includes the following hardware. (1) ani0 to ani7 pins these are the analog input pins of the 8- channel a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin can be used as i/o port pins. (2) sample & hold circuit the sample & hold circuit samples the input voltage of the analog input pin selected by the selector when a/d conversion is started, and holds the samp led voltage value during a/d conversion. (3) series resistor string the series resistor stri ng is connected between av ref and av ss , and generates a voltage to be compared with the sampled voltage value. figure 13-2. circuit configuration of series resistor string adcs series resistor string av ref p-ch av ss (4) voltage comparator the voltage comparator compares the sampled voltage value and the output volt age of the series resistor string. (5) successive approximation register (sar) this register converts the result of comparison by the voltage comparator, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). (6) 10-bit a/d conversion r esult register (adcr) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcr re gister holds the a/d conversion result in its higher 10 bits (the lower 6 bits are fixed to 0).
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 306 (7) 8-bit a/d conversion result register (adcrh) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcrh register stores the higher 8 bi ts of the a/d conversion result. caution when data is read from adcr and adcrh, a wa it cycle is generated. do not read data from adcr and adcrh when the cpu is operating on the subsystem clock and the peripheral hardware clock is stopped. for de tails, see chapter 31 cautions for wait. (8) controller this circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of t he conversion operation. when a/d c onversion has been completed, this controller generates intad. (9) av ref pin this pin inputs an analog power/reference voltage to the a/d converter. make this pin the same potential as the v dd pin when port 2 is used as a digital port. the signal input to ani0 to ani7 is converted into a digital signal, based on the voltage applied across av ref and av ss . (10) av ss pin this is the ground potential pin of the a/d converter. al ways use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. (11) a/d converter mode register (adm) this register is used to set the conver sion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) a/d port configuration register (adpc) this register switches t he ani0/p20 to ani7/p27 pins to analog inpu t of a/d converter or digital i/o of port. (13) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (14) port mode register 2 (pm2) this register switches the ani0/p20 to ani7/p27 pins to input or output.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 307 13.3 registers used in a/d converter the a/d converter uses the following six registers. ? a/d converter mode register (adm) ? a/d port configuration register (adpc) ? analog input channel specification register (ads) ? port mode register 2 (pm2) ? 10-bit a/d conversion result register (adcr) ? 8-bit a/d conversion result register (adcrh) (1) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 13-3. format of a/d converter mode register (adm) adce lv0 note 1 lv1 note 1 fr0 note 1 fr1 note 1 fr2 note 1 0 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 <0> 1 2 3 4 5 6 <7> adm address: ff28h after reset: 00h r/w symbol comparator operation control note 2 stops comparator operation enables comparator operation (comparator: 1/2av ref operation) adce 0 1 notes 1. for details of fr2 to fr0, lv 1, lv0, and a/d conversion, see table 13-2 a/d conversion time selection . 2. the operation of the compar ator is controlled by adcs and adce, and it takes 1 s from operation start to operation stabilization. theref ore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. otherwise, ignore data of the first conversion. table 13-1. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (comparator: 1/2av ref operation, only comparator consumes power) 1 0 conversion mode (comparator operation stopped note ) 1 1 conversion mode (comparator: 1/2av ref operation) note ignore data of the first conversion because it is not guaranteed range.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 308 figure 13-4. timing chart wh en comparator is used adce comparator adcs conversion operation conversion operation conversion stopped conversion waiting comparator: 1/2av ref operation note note to stabilize the internal circuit, the time from the rising of the adce bit to the falling of the adcs bit must be 1 s or longer. cautions 1. a/d conversion must be stopped before re writing bits fr0 to fr2, lv1, and lv0 to values other than the identical data. 2. if data is written to adm, a wait cycle is generated. do not write data to adm when the cpu is operating on the subsystem clock and the periphera l hardware clock is stopped. for details, see chapter 31 cautions for wait.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 309 table 13-2. a/d conversion time selection (1) 2.7 v av ref 5.5 v a/d converter mode register (adm) conversion ti me selection conversion time configuration fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 10 mhz f prs = 20 mhz note conversion clock (f ad ) sar clear sampling successive conversion time adcr transfer, intad generation 0 0 0 0 0 264/f prs 26.4 s 13.2 s note f prs /12 0 0 1 0 0 176/f prs 17.6 s 8.8 s note f prs /8 0 1 0 0 0 132/f prs 13.2 s 6.6 s note f prs /6 0 1 1 0 0 88/f prs setting prohibited 8.8 s note f prs /4 1 0 0 0 0 66/f prs 33.0 s 6.6 s note f prs /3 1 0 1 0 0 44/f prs 22.0 s setting prohibited setting prohibited f prs /2 2/f ad 6/f ad 12/f ad 2/f ad other than above setting prohibited note this can be set only when 4.0 v av ref 5.5 v. (2) 2.3 v av ref < 2.7 v a/d converter mode register (adm) conversion ti me selection conversion time configuration fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 5 mhz conversion clock (f ad ) sar clear sampling successive conversion time adcr transfer, intad generation 0 0 0 0 1 480/f prs setting prohibited f prs /12 0 0 1 0 1 320/f prs 64.0 s f prs /8 0 1 0 0 1 240/f prs 48.0 s f prs /6 0 1 1 0 1 160/f prs setting prohibited 32.0 s f prs /4 1 0 0 0 1 120/f prs 60.0 s setting prohibited f prs /3 1 0 1 0 1 80/f prs 40.0 s setting prohibited f prs /2 2/f ad 24/f ad 12/f ad 2/f ad other than above setting prohibited cautions 1. set the conversion ti mes with the following conditions. ? 4.0 v av ref 5.5 v: sampling + successive c onversion time = 5 to 30 s (f ad = 0.6 to 3.6 mhz) ? 2.7 v av ref < 4.0 v: sampling + successive conversion time = 10 to 30 s (f ad = 0.6 to 1.8 mhz) ? 2.3 v av ref < 2.7 v: sampling + successive conversion time = 25 to 62 s (f ad = 0.6 to 1.48 mhz) 2. when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 3. change lv1 and lv0 from the default value, when 2.3 v av ref < 2.7 v. 4. the above conversion time do es not include clock frequency e rrors. select conversion time, taking clock frequency erro rs into consideration. remark f prs : peripheral hardware clock frequency
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 310 figure 13-5. a/d converter sa mpling and a/d conversion timing adcs wait period note conversion time conversion time sampling time sampling timing intad adcs 1 or ads rewrite sampling time sar clear sar clear transfer to adcr, intad generation successive conversion time note for details of wait period, see chapter 31 cautions for wait . (2) 10-bit a/d conversion r esult register (adcr) this register is a 16-bit register that stores the a/d conversion result. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. the higher 8 bits of the conversion result are stor ed in ff09h and the lower 2 bits are st ored in the higher 2 bits of ff08h. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation sets this register to 0000h. figure 13-6. format of 10-bit a/d conversion result register (adcr) symbol address: ff08h, ff09h after reset: 0000h r ff09h ff08h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm), analog input ch annel specification register (ads), and a/d port configuration register (adpc), the contents of adcr may become undefined. read the conversion resu lt following conversion completion before writing to adm, ads, and adpc. using timing other than the above m ay cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycle is ge nerated. do not read data from adcr when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 31 cautions for wait.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 311 (3) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that stores the a/d conversion result. the higher 8 bits of 10-bit resolution are stored. adcrh can be read by an 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 13-7. format of 8-bit a/d c onversion result register (adcrh) symbol adcrh address: ff09h after reset: 00h r 76543210 cautions 1. when writing to the a/d converter mode register (adm), analog input ch annel specification register (ads), and a/d port configuration register (adpc), the contents of adcrh may become undefined. read the conversion resu lt following conversion completion before writing to adm, ads, and adpc. using timing other than the above m ay cause an incorrect conversion result to be read. 2. if data is read from adcrh, a wait cycle is generated. do not r ead data from adcrh when the cpu is operating on the subsystem clock a nd the peripheral hardware clock is stopped. for details, see chapter 31 cautions for wait.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 312 (4) analog input channel specification register (ads) this register specifies the input channel of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 13-8. format of analog input channel specification register (ads) ads0 ads1 ads2 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads0 0 1 0 1 0 1 0 1 ads1 0 0 1 1 0 0 1 1 ads2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ads address: ff29h after reset: 00h r/w symbol cautions 1. be sure to clear bits 3 to 7 to 0. 2 set a channel to be used for a/d conversion in the input mode by usi ng port mode register 2 (pm2). 3. do not set a pin to be used as a digital i/o pin with adpc with ads. 4. if data is written to ads, a wait cycle is generated. do not wr ite data to ads when the cpu is operating on the subsystem clock and the periphera l hardware clock is stopped. for details, see chapter 31 cautions for wait.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 313 (5) a/d port configuration register (adpc) this register switches t he ani0/p20 to ani7/p27 pins to analog inpu t of a/d converter or digital i/o of port. adpc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 13-9. format of a/d port configuration register (adpc) adpc0 adpc1 adpc2 adpc3 0 0 0 0 analog input (a)/digital i/o (d) switching setting prohibited adpc3 0 1 2 3 4 5 6 7 adpc address: ff2fh after reset: 00h r/w symbol ani7/ p27 a a a a a a a a d ani6/ p26 a a a a a a a d d ani5/ p25 a a a a a a d d d ani4/ p24 a a a a a d d d d ani3/ p23 a a a a d d d d d ani2/ p22 a a a d d d d d d ani1/ p21 a a d d d d d d d ani0/ p20 a d d d d d d d d 0 0 0 0 0 0 0 0 1 adpc2 0 0 0 0 1 1 1 1 0 adpc1 0 0 1 1 0 0 1 1 0 adpc0 0 1 0 1 0 1 0 1 0 other than above cautions 1. set a channel to be u sed for a/d conversion in the input mode by usi ng port mode register 2 (pm2). 2. do not set a pin to be used as a digital i/o pin with adpc with ads. 3. if data is written to adpc, a wait cycle is ge nerated. do not write data to adpc when the cpu is operating on the subsystem clock and the peri pheral hardware clock is stopped. for details, see chapter 31 cautions for wait.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 314 (6) port mode register 2 (pm2) when using the ani0/p20 to ani7/p27 pins for analog input port, set pm20 to pm27 to 1. the output latches of p20 to p27 at this time may be 0 or 1. if pm20 to pm27 are set to 0, they cannot be used as analog input port pins. pm2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 13-10. format of port mode register 2 (pm2) pm20 pm21 pm22 pm23 pm24 pm25 pm26 pm27 p2n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) pm2n 0 1 0 1 2 3 4 5 6 7 pm2 address: ff22h after reset: ffh r/w symbol ani0/p20 to ani7/p27 pins are as shown below depending on the settings of adpc, ads, and pm2. table 13-3. setting functions of ani0/p20 to ani7/p27 pins adpc pm2 ads ani0/p20 to ani7/p27 pin selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited selects ani. setting prohibited input mode does not select ani. digital input selects ani. setting prohibited digital i/o selection output mode does not select ani. digital output
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 315 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1 to start the operation of the comparator. <2> set channels for a/d conversion to analog input by usi ng the a/d port configuration register (adpc) and set to input mode by using port mode register 2 (pm2). <3> set a/d conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm. <4> select one channel for a/d conversion using the analog input channel specification register (ads). <5> start the conversion operation by setting bit 7 (adcs) of adm to 1. (<6> to <12> are operations performed by hardware.) <6> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <7> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the sampled voltage is held until the a/ d conversion operation has ended. <8> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <9> the voltage difference between the series resistor st ring voltage tap and sampled voltage is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <10> next, bit 8 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and sampled voltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <11> comparison is continued in this way up to bit 0 of sar. <12> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <13> repeat steps <6> to <12>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the st atus of adce = 1, start from <5>. to start a/d conversion again when adce = 0, set adce to 1, wait for 1 s or longer, and start <5>. to change a channel of a/d conversion, start from <4>. caution make sure the period of <1> to <5> is 1 s or more. remark two types of a/d conversion re sult registers are available. ? adcr (16 bits): store 10-bit a/d conversion value ? adcrh (8 bits): store 8-bit a/d conversion value
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 316 figure 13-11. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of t he a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to the analog input chan nel specification register (ads) during an a/d conversion operation, the conversion operation is in itialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset signal generation sets the a/d conversion re sult register (adcr, adcrh) to 0000h or 00h.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 317 13.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the theoretical a/d conversion result (stored in the 10-bit a/d conver sion result register (adcr)) is shown by the following expression. sar = int ( 1024 + 0.5) adcr = sar 64 or ( ? 0.5) v ain < ( + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: a/d conversion result register (adcr) value sar: successive approximation register figure 13-12 shows the relationship between the analo g input voltage and the a/d conversion result. figure 13-12. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h a/d conversion result sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 v ain av ref av ref 1024 av ref 1024 adcr 64 adcr 64
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 318 13.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channe l of analog input is selected from ani0 to ani7 by the analog input channel specification register (ads) and a/d co nversion is executed. (1) a/d conversion operation by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specif ied by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d c onversion is stored in t he a/d conversion result register (adcr), and an interrupt request signal (int ad) is generated. when one a/d conversion has been completed, the next a/d conversion oper ation is immediately started. if ads is rewritten during a/d conversion, the a/d conv ersion operation under execut ion is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conv ersion is immediately stopped. at this time, the conversion result immediat ely before is retained. figure 13-13. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped conversion result immediately before is retained a/d conversion adcr, adcrh intad conversion is stopped conversion result immediately before is retained remarks 1. n = 0 to 7 2. m = 0 to 7
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 319 the setting methods are described below. <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> set the channel to be used in the analog input m ode by using bits 3 to 0 (adpc3 to adpc0) of the a/d port configuration register (adpc) and bits 7 to 0 (pm27 to pm20) of port mode register 2 (pm2). <3> select conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm. <4> select a channel to be used by using bits 2 to 0 (ads2 to ads0) of the analog input channel specification register (ads). <5> set bit 7 (adcs) of adm to 1 to start a/d conversion. <6> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <7> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). <8> change the channel using bits 2 to 0 (ads 2 to ads0) of ads to start a/d conversion. <9> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <10> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). <11> clear adcs to 0. <12> clear adce to 0. cautions 1. make sure the period of <1> to <5> is 1 s or more. 2. <1> may be done between <2> and <4>. 3. <1> can be omitted. howe ver, ignore data of the first con version after <5> in this case. 4. the period from <6> to <9> differs from the conversion time set using bits 5 to 1 (fr2 to fr0, lv1, lv0) of adm. the period from <8> to <9> is the conversion time set using fr2 to fr0, lv1, and lv0.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 320 13.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 13-14. overall error figur e 13-15. quanti zation error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 321 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion charac teristics deviate from the ideal linear relationship. it expresses the maximum value of the di fference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. figure 13-16. zero-scale error figure 13-17. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 13-18. integral linearity error figure 13-19. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 322 13.6 cautions for a/d converter (1) operating current in stop mode the a/d converter stops operating in the stop mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0. to restart from the standby status, clear bit 0 (adif) of interrupt request flag register 1l (if1l) to 0 and start operation. (2) input range of ani0 to ani7 observe the rated range of the ani0 to an i7 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result regist er (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion adcr or adcrh read has priority. after the read op eration, the new co nversion result is written to adcr or adcrh. <2> conflict between adcr or adcrh write and a/d converter mode regi ster (adm) write, analog input channel specification register (ads), or a/d port configuration register (a dpc) write upon the end of conversion adm, ads, or adpc write has priority. adcr or adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 10-bit resolution, attent ion must be paid to noise input to the av ref pin and pins ani0 to ani7. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external c as shown in figure 13-20 is recommended. <3> do not switch these pins wit h other pins during conversion. <4> the accuracy is improved if the halt mode is set immediately after the start of conversion.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 323 figure 13-20. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani7 (5) ani0/p20 to ani7/p27 <1> the analog input pins (ani0 to ani7) are also used as input port pins (p20 to p27). when a/d conversion is performed with any of ani0 to ani7 selected, do not access p20 to p27 while conversion is in progress; otherwis e the conversion resolution may be degraded. it is recommended to select pins used as p20 to p27 starting wit h the ani0/p20 that is the furthest from av ref . <2> if a digital pulse is applied to the pins adjacent to t he pins currently used for a/ d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. t herefore, do not apply a pulse to the pins adjacent to the pi n undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current fl ows when sampling is not in progre ss, and a current that charges the capacitor flows during sampling. consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the ou tput impedance of the analog input source to within 10 k ? , and to connect a capacitor of about 100 pf to the ani0 to ani7 pins (see figure 13- 20 ). (7) av ref pin input impedance a series resistor string of several tens of k ? is connected between the av ref and av ss pins. therefore, if the output impedance of t he reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 324 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 13-21. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 7 2. m = 0 to 7 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if t he adcs bit is set to 1 with the adce bit = 0. take measures such as pollin g the a/d conversion end interrupt r equest (intad) and removing the first conversion result. (10) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to the a/d conver ter mode register (adm), analog input channel specification register (ads), and a/ d port configuration register (adp c), the contents of adcr and adcrh may become undefined. read the conversion re sult following conversion completion before writing to adm, ads, and adpc. using a timing other than the above may cause an incorrect conversion result to be read.
chapter 13 a/d converter preliminary user?s manual u17260ej3v1ud 325 (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 13-22. internal equi valent circuit of anin pin anin c1 c2 r1 table 13-4. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 c1 c2 4.0 v av ref 5.5 v 8.1 k ? 8 pf 5 pf 2.7 v av ref < 4.0 v 31 k ? 8 pf 5 pf 2.3 v av ref < 2.7 v 381 k ? 8 pf 5 pf remarks 1. the resistance and capacitance values shown in table 13-4 are not guaranteed values. 2. n = 0 to 7
preliminary user?s manual u17260ej3v1ud 326 chapter 14 serial interface uart0 14.1 functions of serial interface uart0 serial interface uart0 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode the functions of this mode are outlined below. for details, see 14.4.2 asynchronous seri al interface (uart) mode and 14.4.3 dedicated baud rate generator . ? maximum transfer rate: 312.5 kbps ? two-pin configuration t x d0: transmit data output pin r x d0: receive data input pin ? length of communication data can be selected from 7 or 8 bits. ? dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performe d independently (full-duplex operation). ? fixed to lsb-first communication cautions 1. if clock supply to serial interface uart0 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart0 is stopped (e.g., in the stop mode), each register stops operating, and hold s the value immediatel y before clock supply was stopped. the t x d0 pin also holds the value imme diately before clock supply was stopped and outputs it. however, the operati on is not guaranteed after clock supply is resumed. therefore, reset the circuit so th at power0 = 0, rxe0 = 0, and txe0 = 0. 2. set power0 = 1 and then set txe0 = 1 (tr ansmission) or rxe0 = 1 (reception) to start communication. 3. txe0 and rxe0 are synch ronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least tw o clocks of base clock after txe0 or rxe0 has been clear ed to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission ci rcuit or reception circui t may not be initialized. 4. set transmit data to t xs0 at least one base clock (f xclk0 ) after setting txe0 = 1.
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 327 14.2 configuration of serial interface uart0 serial interface uart0 includes the following hardware. table 14-1. configurati on of serial interface uart0 item configuration registers receive buffer register 0 (rxb0) receive shift register 0 (rxs0) transmit shift register 0 (txs0) control registers asynchronous serial interface o peration mode register 0 (asim0) asynchronous serial interface recepti on error status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 1 (pm1) port register 1 (p1)
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 328 figure 14-1. block diagram of serial interface uart0 t x d0/ sck10/p10 intst0 r x d0/ si10/p11 intsr0 f prs /2 5 f prs /2 3 f prs /2 transmit shift register 0 (txs0) receive shift register 0 (rxs0) receive buffer register 0 (rxb0) asynchronous serial interface reception error status register 0 (asis0) asynchronous serial interface operation mode register 0 (asim0) baud rate generator control register 0 (brgc0) 8-bit timer/ event counter 50 output registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit output latch (p10) pm10 7 7
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 329 (1) receive buffer register 0 (rxb0) this 8-bit register stores parallel data conv erted by receive shift register 0 (rxs0). each time 1 byte of data has been received, new receive dat a is transferred to this r egister from receive shift register 0 (rxs0). if the data length is set to 7 bits the receive data is tran sferred to bits 0 to 6 of rxb0 and the msb of rxb0 is always 0. if an overrun error (ove0) occurs, the rece ive data is not transferred to rxb0. rxb0 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset signal generation and power0 = 0 set this register to ffh. (2) receive shift register 0 (rxs0) this register converts the serial data input to the r x d0 pin into parallel data. rxs0 cannot be directly manipulated by a program. (3) transmit shift register 0 (txs0) this register is used to set transmit data. transmission is started when data is written to txs0, and serial data is transmitted from the t x d0 pins. txs0 can be written by an 8-bit memory manipulatio n instruction. this register cannot be read. reset signal generation, power0 = 0, and txe0 = 0 set this register to ffh. cautions 1. set transmit data to txs0 at least one base clock (f xclk0 ) after setting txe0 = 1. 2. do not write the next transmit data to t xs0 before the transmissi on completion interrupt signal (intst0) is generated.
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 330 14.3 registers controlling serial interface uart0 serial interface uart0 is controlled by the following five registers. ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface recept ion error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface ope ration mode register 0 (asim0) this 8-bit register controls the serial comm unication operations of serial interface uart0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. figure 14-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (1/2) address: ff70h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception. notes 1. the input from the r x d0 pin is fixed to high level when power0 = 0. 2. asynchronous serial interface reception error status register 0 (asis0), transmit shift register 0 (txs0), and receive buffer register 0 (rxb0) are reset.
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 331 figure 14-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (2/2) ps01 ps00 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface reception error status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set power0 to 1 and then set txe0 to 1. to stop the transmission, clear txe0 to 0, and then clear power0 to 0. 2. to start the reception, set power0 to 1 and th en set rxe0 to 1. to stop the reception, clear rxe0 to 0, and then clear power0 to 0. 3. set power0 to 1 and then set rxe0 to 1 wh ile a high level is input to the rxd0 pin. if power0 is set to 1 and rxe0 is set to 1 wh ile a low level is input, reception is started. 4. txe0 and rxe0 are synch ronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least two cl ocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or recepti on circuit may not be initialized. 5. set transmit data to t xs0 at least one base clock (f xclk0 ) after setting txe0 = 1. 6. clear the txe0 and rxe0 bits to 0 be fore rewriting the ps01, ps00, and cl0 bits. 7. make sure that txe0 = 0 when rewriting th e sl0 bit. reception is always performed with ?number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit. 8. be sure to set bit 0 to 1.
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 332 (2) asynchronous serial interface recepti on error status register 0 (asis0) this register indicates an error status on completion of re ception by serial interface uart0. it includes three error flag bits (pe0, fe0, ove0). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation sets this register to 00h if bi t 7 (power0) and bit 5 (rxe0) of asim0 = 0. 00h is read when this register is read. if a reception error occurs, read asis0 and then read receive buffer register 0 (rxb0) to clear the error flag. figure 14-3. format of asynchronous serial inte rface reception error status register 0 (asis0) address: ff73h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis0 0 0 0 0 0 pe0 fe0 ove0 pe0 status flag indicating parity error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb0 register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface operati on mode register 0 (asim0). 2. only the first bit of the receive data is checked as the stop bit, re gardless of the number of stop bits. 3. if an overrun error occurs , the next receive data is not wr itten to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. do not read data from asis0 when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 31 cautions for wait.
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 333 (3) baud rate generator c ontrol register 0 (brgc0) this register selects the base clock of serial interf ace uart0 and the division value of the 5-bit counter. brgc0 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 1fh. figure 14-4. format of baud rate ge nerator control register 0 (brgc0) address: ff71h after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 base clock (f xclk0 ) selection tps01 tps00 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 tm50 output note 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 1 0 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 1 1 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 0 0 setting prohibited 0 1 0 0 0 8 f xclk0 /8 0 1 0 0 1 9 f xclk0 /9 0 1 0 1 0 10 f xclk0 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 1 0 26 f xclk0 /26 1 1 0 1 1 27 f xclk0 /27 1 1 1 0 0 28 f xclk0 /28 1 1 1 0 1 29 f xclk0 /29 1 1 1 1 0 30 f xclk0 /30 1 1 1 1 1 31 f xclk0 /31 note note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/ event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/ event counter 50 first and then set t he count clock to make the duty = 50%. it is not necessary to enable the to50 pin as a timer output pin in any mode.
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 334 cautions 1. make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. 2. the baud rate value is the output clock of the 5-bit c ounter divided by 2. remarks 1. f xclk0 : frequency of base clock selected by the tps01 and tps00 bits 2. f prs : peripheral hardware clock frequency 3. k: value set by the mdl04 to md l00 bits (k = 8, 9, 10, ..., 31) 4. : don?t care 5. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 (4) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p10/txd0/sck10 pin for serial interface dat a output, clear pm10 to 0 and set the output latch of p10 to 1. when using the p11/rxd0/si10 pin for seri al interface data input, set pm11 to 1. the output latch of p11 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 14-5. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 335 14.4 operation of serial interface uart0 serial interface uart0 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 14.4.1 operation stop mode in this mode, serial communication cannot be executed, thus reducing the power consumption. in addition, the pins can be used as ordinary port pins in this mode. to se t the operation stop mode, clear bits 7, 6, and 5 (power0, txe0, and rxe0) of asim0 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 0 (asim0). asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff70h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe0 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). rxe0 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the input from the r x d0 pin is fixed to high level when power0 = 0. 2. asynchronous serial interface reception error status register 0 (asis0), transmit shift register 0 (txs0), and receive buffer register 0 (rxb0) are reset. caution clear power0 to 0 after clearing txe0 and rxe0 to 0 to set the operation stop mode. to start the communication, set power0 to 1, and then set txe0 or rxe0 to 1. remark to use the rxd0/si10/p11 and txd0/sck10/p 10 pins as general-purpose port pins, see chapter 5 port functions .
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 336 14.4.2 asynchronous serial interface (uart) mode in this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface recept ion error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) ? port mode register 1 (pm1) ? port register 1 (p1) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the brgc0 register (see figure 14-4 ). <2> set bits 1 to 4 (sl0, cl0, ps00, and ps01) of the asim0 register (see figure 14-2 ). <3> set bit 7 (power0) of the asim0 register to 1. <4> set bit 6 (txe0) of the asim0 register to 1. transmission is enabled. set bit 5 (rxe0) of the asim0 register to 1. reception is enabled. <5> write data to the txs0 register. data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 14-2. relationship between register settings and pins pin function power0 txe0 rxe0 pm10 p10 pm11 p11 uart0 operation txd0/sck10/p10 rxd0/si10/p11 0 0 0 note note note note stop sck10/p10 si10/p11 0 1 note note 1 reception sck10/p10 rxd0 1 0 0 1 note note transmission txd0 si10/p11 1 1 1 0 1 1 transmission/ reception txd0 rxd0 note can be set as port function or serial interface csi10. remark : don?t care power0: bit 7 of asynchronous serial interface operation mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 pm1 : port mode register p1 : port output latch
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 337 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. figure 14-6. format of normal uart transmit/receive data start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits (lsb first) ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (asim0). figure 14-7. example of normal uart transmit/receive data waveform 1. data length: 8 bits, parity: even pari ty, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 7 bits, parity: odd parity , stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 3. data length: 8 bits, pa rity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 338 (b) parity types and operation the parity bit is used to detect a bit error in communicati on data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur.
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 339 (c) transmission if bit 7 (power0) of asynchronous serial interface op eration mode register 0 (asim0) is set to 1 and bit 6 (txe0) of asim0 is then set to 1, transmission is enabl ed. transmission can be star ted by writing transmit data to transmit shift register 0 (txs0). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the start bit is output from the t x d0 pin, and the transmit data is output followed by the rest of the data in order starting from the lsb. when tr ansmission is completed, the parity and stop bits set by asim0 are appended and a transmi ssion completion interrupt request (intst0) is generated. transmission is stopped until the data to be transmitted next is written to txs0. figure 14-8 shows the timing of the transmission comp letion interrupt request (intst0). this interrupt occurs as soon as the last stop bit has been output. caution after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. figure 14-8. transmission comple tion interrupt request timing 1. stop bit length: 1 intst0 d0 start d1 d2 d6 d7 stop t x d0 (output) parity 2. stop bit length: 2 t x d0 (output) intst0 d0 start d1 d2 d6 d7 parity stop
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 340 (d) reception reception is enabled and the r x d0 pin input is sampled when bit 7 (power0) of asynchronous serial interface operation mode register 0 (asim0) is set to 1 and then bit 5 (rxe0) of asim0 is set to 1. the 5-bit counter of the baud rate generator st arts counting when the falling edge of the r x d0 pin input is detected. when the set value of baud rate generator control register 0 (brgc0) has been counted, the r x d0 pin input is sampled again ( in figure 14-9). if the r x d0 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, recept ion is started, and serial data is sequentially stored in receive shift register 0 (rxs0) at the set baud rate. when the st op bit has been received, the reception completion interrupt (intsr0) is generated and t he data of rxs0 is written to receive buffer register 0 (rxb0). if an overrun error (ove0) occurs, however, the receive data is not written to rxb0. even if a parity error (pe0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an recepti on error interrupt (intsr0) is generat ed after completion of reception. intsr0 occurs upon completion of reception and in case of a reception error. figure 14-9. reception completi on interrupt request timing r x d0 (input) intsr0 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb0 cautions 1. if a reception erro r occurs, read asynchronous serial interface receptio n error status register 0 (asis0) and then read receive buffe r register 0 (rxb0) to clear the error flag. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ?num ber of stop bits = 1? . the second stop bit is ignored.
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 341 (e) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 0 (asis0) is set as a result of data reception, a reception error inte rrupt (intsr0) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis0 in the reception error interrupt (intsr0) servicing (see figure 14-3 ). the contents of asis0 are cleared to 0 when asis0 is read. table 14-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 0 (rxb0). (f) noise filter of receive data the r x d0 signal is sampled using the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 14- 10, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 14-10. noise filter circuit internal signal b internal signal a match detector in base clock r x d0/si10/p11 q in ld_en q
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 342 14.4.3 dedicated baud rate generator the dedicated baud rate generator consis ts of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of uart0. separate 5-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 7 and 6 (tps01 and tps00) of baud rate generator control register 0 (brgc0) is supplied to each module when bit 7 (power0) of asyn chronous serial interface operation mode register 0 (asim0) is 1. this clock is called the base clock and its frequency is called f xclk0 . the base clock is fixed to low level when power0 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power0) or bit 6 (txe0) of asynchronous serial interface operation mode register 0 (asim0) is 0. it starts counting when power0 = 1 and txe0 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit shift register 0 (txs0). ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power0) or bit 5 (rxe0) of asynchronous serial interface operation mode register 0 (asim0) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. figure 14-11. configuration of baud rate generator f xclk0 selector power0 5-bit counter match detector baud rate brgc0: mdl04 to mdl00 1/2 power0, txe0 (or rxe0) brgc0: tps01, tps00 8-bit timer/ event counter 50 output f prs /2 5 f prs /2 f prs /2 3 baud rate generator remark power0: bit 7 of asynchronous serial interface operation mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 brgc0: baud rate generator control register 0
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 343 (2) generation of serial clock a serial clock to be generated can be specified by usi ng baud rate generator control register 0 (brgc0). select the clock to be input to the 5-bit counter by using bits 7 and 6 (tps01 and tps00) of brgc0. bits 4 to 0 (mdl04 to mdl00) of brgc0 can be used to select the division value (f xclk0 /8 to f xclk0 /31) of the 5-bit counter. table 14-4. set value of tps01 and tps00 base clock (f xclk0 ) selection tps01 tps00 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 tm50 output 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 1 0 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 1 1 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz (a) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk0 : frequency of base clock selected by the tps 01 and tps00 bits of the brgc0 register k: value set by the mdl04 to mdl00 bits of t he brgc0 register (k = 8, 9, 10, ..., 31) (b) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate ra nge during reception. example: frequency of base clock = 2.5 mhz = 2,500,000 hz set value of mdl04 to mdl00 bits of brgc0 register = 10000b (k = 16) target baud rate = 76,800 bps baud rate = 2.5 m/(2 16) = 2,500,000/(2 16) = 78,125 [bps] error = (78,125/76,800 ? 1) 100 = 1.725 [%] f xclk0 2 k actual baud rate (baud rate with error) desired baud rate (correct baud rate)
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 344 (3) example of setting baud rate table 14-5. set data of baud rate generator f prs = 2.0 mhz f prs = 5.0 mhz f prs = 10.0 mhz f prs = 20.0 mhz baud rate [bps] tps01, tps00 k calculated value err [%] tps01, tps00 k calculated value err [%] tps01, tps00 k calculated value err [%] tps01, tps00 k calculated value err [%] 4800 2 26 4808 0.16 3 16 4883 1.73 ? ? ? ? ? ? ? ? 9600 2 13 9615 0.16 3 8 9766 1.73 3 16 9766 1.73 ? ? ? ? 10400 2 12 10417 0.16 2 30 10417 0.16 3 15 10417 0.16 3 30 10417 0.16 19200 1 26 19231 0.16 2 16 19531 1.73 3 8 19531 1.73 3 16 19531 1.73 24000 1 21 23810 ? 0.79 2 13 24038 0.16 2 26 24038 0.16 3 13 24038 0.16 31250 1 16 31250 0 2 10 31250 0 2 20 31250 0 3 10 31250 0 33660 1 15 33333 ? 0.79 2 9 34722 3.34 2 18 34722 3.34 3 9 34722 3.34 38400 1 13 38462 0.16 2 8 39063 1.73 2 16 39063 1.73 3 8 39063 1.73 56000 1 9 55556 ? 0.79 1 22 56818 1.46 2 11 56818 1.46 2 22 56818 1.46 62500 1 8 62500 0 1 20 62500 0 2 10 62500 0 2 20 62500 0 76800 ? ? ? ? 1 16 78125 1.73 2 8 78125 1.73 2 16 78125 1.73 115200 ? ? ? ? 1 11 113636 ? 1.36 1 22 113636 ? 1.36 2 11 113636 ? 1.36 153600 ? ? ? ? 1 8 156250 1.73 1 16 156250 1.73 2 8 156250 1.73 remark tps01, tps00: bits 7 and 6 of baud rate generator control register 0 (brgc0) (setting of base clock (f xclk0 )) k: value set by the mdl04 to mdl00 bits of brgc0 (k = 8, 9, 10, ..., 31) f prs : peripheral hardware clock frequency err: baud rate error
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 345 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 14-12. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart0 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 14-12, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 0 (brgc0) a fter the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart0 k: set value of brgc0 fl: 1-bit data length margin of latch timing: 2 clocks
chapter 14 serial interface uart0 preliminary user?s manual u17260ej3v1ud 346 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 14-6. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 8 +3.53% ? 3.61% 16 +4.14% ? 4.19% 24 +4.34% ? 4.38% 31 +4.44% ? 4.47% remarks 1. the permissible error of reception depends on t he number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc0 k ? 2 2k 21k + 2 2k 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2
preliminary user?s manual u17260ej3v1ud 347 chapter 15 serial interface uart6 15.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 15.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 15.4.2 asynchronous seri al interface (uart) mode and 15.4.3 dedicated baud rate generator . ? maximum transfer rate: 312.5 kbps ? two-pin configuration t x d6: transmit data output pin r x d6: receive data input pin ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performe d independently (full duplex operation). ? msb- or lsb-first communication selectable ? inverted transmission operation ? sync break field transmission from 13 to 20 bits ? more than 11 bits can be identified for sync break field reception (sbf reception flag provided). cautions 1. the t x d6 output inversion function inverts only th e transmission side a nd not the reception side. to use this f unction, the reception side must be ready for reception of inverted data. 2. if clock supply to serial interface uart6 is not stopped (e .g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and hold s the value immediatel y before clock supply was stopped. the t x d6 pin also holds the value imme diately before clock supply was stopped and outputs it. however, the operati on is not guaranteed after clock supply is resumed. therefore, reset the circuit so th at power6 = 0, rxe6 = 0, and txe6 = 0. 3. set power6 = 1 and then set txe6 = 1 (tr ansmission) or rxe6 = 1 (reception) to start communication. 4. txe6 and rxe6 are sync hronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or r xe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or reception circui t may not be initialized. 5. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. 6. if data is continuously tr ansmitted, the communicat ion timing from the stop bit to the next start bit is extended two operating clocks of the macro. however, th is does not affect the result of communication because the reception side initializ es the timing when it has detected a start bit. do no t use the continuous transmissi on function if the interface is incorporated in lin.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 348 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to contro l the switches, actuator s, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master tr ansmits a frame with baud rate information and the slave receives it and corrects the baud rate error. theref ore, communication is possible when the baud rate error in the slave is 15% or less. figures 15-1 and 15-2 outline the transmissi on and reception operations of lin. figure 15-1. lin transmission operation lin bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit note 2 sbf transmission sync break field sync field identifier field data field data field checksum field tx6 (output) intst6 note 3 notes 1. the wakeup signal frame is substituted by 80h transmission in the 8-bit mode. 2. the sync break field is output by har dware. the output width is the bit length set by bits 4 to 2 (sbl62 to sbl60) of asynchronous serial inte rface control register 6 (asicl6) (see 15.4.2 (2) (h) sbf transmission ). 3. intst6 is output on completion of each transmissi on. it is also output when sbf is transmitted. remark the interval between each field is controlled by software.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 349 figure 15-2. lin reception operation lin bus 13-bit sbf reception sf reception id reception data reception data reception data reception wakeup signal frame sync break field sync field identifier field data field data field checksum field r x d6 (input) reception interrupt (intsr6) edge detection (intp0) capture timer disable enable disable enable <1> <2> <3> <4> <5> reception processing is as follows. <1> the wakeup signal is detected at the edge of t he pin, and enables uart6 and sets the sbf reception mode. <2> reception continues until the stop bi t is detected. when an sbf with low- level data of 11 bits or more has been detected, it is assum ed that sbf reception has been complet ed correctly, and an interrupt signal is output. if an sbf with low-level dat a of less than 11 bits has been detect ed, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. <3> if sbf reception has been completed correctly, an interru pt signal is output. start 16-bit timer/event counter 00 by the sbf reception end interrupt servicing and meas ure the bit interval (pulse width) of the sync field (see 7.4.8 pulse width measurement operation ). detection of errors ove6, pe6, and fe6 is suppressed, and error detection proc essing of uart communication and dat a transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. <4> calculate the baud rate error from the bit interval of the sync field, disable ua rt6 after sf reception, and then re-set baud rate generator control register 6 (brgc6). <5> distinguish the checksum field by software. also perform processing by software to initialize uart6 after reception of the checksum field and to set the sbf reception mode again. figure 15-3 shows the port configurat ion for lin reception operation. the wakeup signal transmitted from the lin master is received by detecting the edge of the external interrupt (intp0). the length of the sync field transmitted from the lin master can be measured using the external event capture operation of 16-bit timer/event counte r 00, and the baud rate error can be calculated. the input source of t he reception port input (r x d6) can be input to the external interrupt (intp0) and 16-bit timer/event counter 00 by port input swit ch control (isc0/isc1), without connecting r x d6 and intp0/ti000 externally.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 350 figure 15-3. port configurati on for lin reception operation rxd6 input intp0 input ti000 input p14/rxd6 p120/intp0/exlvi p00/ti000 port input switch control (isc0) 0: select intp0 (p120) 1: select rxd6 (p14) port mode (pm14) output latch (p14) port mode (pm120) output latch (p120) port input switch control (isc1) 0: select ti000 (p00) 1: select rxd6 (p14) selector selector selector selector selector port mode (pm00) output latch (p00) remark isc0, isc1: bits 0 and 1 of the input switch control register (isc) (see figure 15-11 ) the peripheral functions used in the lin communication operation are shown below. ? external interrupt (intp0); wakeup signal detection use: detects the wakeup signal edges and detects start of communication. ? 16-bit timer/event counter 00 (ti000); baud rate error detection use: detects the baud rate error (meas ures the ti000 input edge interval in the capture mode) by detecting the sync field (sf) length and divides it by the number of bits. ? serial interface uart6
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 351 15.2 configuration of serial interface uart6 serial interface uart6 includes the following hardware. table 15-1. configurati on of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface o peration mode register 6 (asim6) asynchronous serial interface recepti on error status register 6 (asis6) asynchronous serial interface transm ission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6) input switch control register (isc) port mode register 1 (pm1) port register 1 (p1)
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 352 figure 15-4. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/ p13 intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/ p14 ti000, intp0 note intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) output latch (p13) pm13 8 selector note selectable with input switch control register (isc).
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 353 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive data is transferred to this register from rxs6. if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the rece ive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset signal generation sets this register to ffh. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. tr ansmission is started when data is written to txb6. this register can be read or written by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. cautions 1. do not write data to txb6 when bi t 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. 2. do not refresh (write the same value to) txb6 by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asynchr onous serial interface operation mode register 6 (asim6) are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1). 3. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is written for the first tr ansmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. da ta is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the base clock. txs6 cannot be directly manipulated by a program.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 354 15.3 registers controlling serial interface uart6 serial interface uart6 is controlle d by the following nine registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface ope ration mode register 6 (asim6) this 8-bit register controls the serial comm unication operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. remark asim6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (1/2) address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 enables operation of t he internal operation clock txe6 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception notes 1. the output of the t x d6 pin goes high level and the input from the r x d6 pin is fixed to the high level when power6 = 0 during transmission. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 355 figure 15-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) ps61 ps60 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set power6 to 1 and then set txe6 to 1. to stop the transmission, clear txe6 to 0, and then clear power6 to 0. 2. to start the reception, set power6 to 1 and th en set rxe6 to 1. to stop the reception, clear rxe6 to 0, and then clear power6 to 0. 3. set power6 to 1 and then set rxe6 to 1 while a high level is input to the r x d6 pin. if power6 is set to 1 and rxe6 is set to 1 wh ile a low level is input, reception is started. 4. txe6 and rxe6 are synch ronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or r xe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or reception circui t may not be initialized. 5. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. 6. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 7. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 8. clear txe6 to 0 before re writing the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 9. make sure that rxe6 = 0 when rewriting the isrm6 bit.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 356 (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of re ception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation sets this register to 00h if bi t 7 (power6) and bit 5 (rxe6) of asim6 = 0. 00h is read when this register is read. if a reception error occurs, read asis6 and then read receive buffer register 6 (rxb6) to clear the error flag. figure 15-6. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb6 register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. the first bit of the receive da ta is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs , the next receive data is not wr itten to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. do not read data from asis6 when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 31 cautions for wait.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 357 (3) asynchronous serial interface tran smission status register 6 (asif6) this register indicates the status of transmission by se rial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset signal generation sets this register to 00h if bit 7 (power6) and bit 6 (txe6) of asim6 = 0. figure 15-7. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data conti nuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to th e txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0 ? after generation of the tran smission completion interrupt, and then execute initializat ion. if initiali zation is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 358 (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark cksr6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-8. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection tps63 tps62 tps61 tps60 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs 2 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz 0 1 1 0 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 15.625 khz 39.06 khz 78.13 khz 156.25 khz 1 0 0 0 f prs /2 8 7.813 khz 19.53 khz 39.06 khz 78.13 khz 1 0 0 1 f prs /2 9 3.906 khz 9.77 khz 19.53 khz 39.06 khz 1 0 1 0 f prs /2 10 1.953 khz 4.88 khz 9.77 khz 19.53 khz 1 0 1 1 tm50 output note other than above setting prohibited note note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/ event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/ event counter 50 first and then set t he count clock to make the duty = 50%. it is not necessary to enable the to50 pin as a timer output pin in any mode. caution make sure power6 = 0 wh en rewriting tps63 to tps60. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 359 (5) baud rate generator c ontrol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. remark brgc6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-9. format of baud rate ge nerator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 setting prohibited 0 0 0 0 1 0 0 0 8 f xclk6 /8 0 0 0 0 1 0 0 1 9 f xclk6 /9 0 0 0 0 1 0 1 0 10 f xclk6 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the t ps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 8, 9, 10, ..., 255) 3. : don?t care
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 360 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 16h. caution asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). however, do not set bot h sbrt6 and sbtt6 to 1 by a refresh operation during sbf reception (sbrt6 = 1) or sbf transm ission (until intst6 o ccurs since sbtt6 has been set (1)), because it may re-trigge r sbf reception or sbf transmission. figure 15-10. format of asynchronous serial interface control register 6 (asicl6) (1/2) address: ff58h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger note bit 7 is read-only.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 361 figure 15-10. format of asynchronous serial interface control register 6 (asicl6) (2/2) sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir6 first-bit specification 0 msb 1 lsb txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 cautions 1. in the case of an sbf reception error, the mode return s to the sbf reception mode. the status of the sbrf6 flag is held (1). 2. before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. after setting the sbrt6 bit to 1, do not clear it to 0 before sbf reception is completed (before an interrupt request signal is generated). 3. the read value of the sbrt6 bit is always 0. sbrt6 is auto matically cleared to 0 after sbf reception has been co rrectly completed. 4. before setting the sbtt6 bit to 1, make sure that bit 7 (pow er6) and bit 6 (txe6) of asim6 = 1. after setting the sbtt6 bit to 1, do not clear it to 0 before sbf transmission is completed (before an interrupt requ est signal is generated). 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically clear ed to 0 at the end of sbf transmission. 6. do not set the sbrt6 bit to 1 during reception, and do not set the sbtt6 bit to 1 during transmission. 7. before rewriting the dir6 and txdlv6 bits, clear the txe6 a nd rxe6 bits to 0.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 362 (7) input switch control register (isc) the input switch control regi ster (isc) is used to receive a status si gnal transmitted from the master during lin (local interconnect network) reception. the signal input from the p14/r x d6 pin is selected as the input sour ce of intp0 and ti000 when isc0 and isc1 are set to 1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 15-11. format of input s witch control register (isc) address: ff4fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 ti000 input source selection 0 ti000 (p00) 1 r x d6 (p14) isc0 intp0 input source selection 0 intp0 (p120) 1 r x d6 (p14) (8) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p13/t x d6 pin for serial interface data output, clear pm 13 to 0 and set the output latch of p13 to 1. when using the p14/r x d6 pin for serial interface data input, set pm14 to 1. the output latch of p14 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 15-12. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 363 15.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 15.4.1 operation stop mode in this mode, serial communication cannot be executed; theref ore, the power consumption can be reduced. in addition, the pins can be used as ordinary po rt pins in this mode. to set the operation stop mode, clear bits 7, 6, and 5 (power6, txe6, and rxe6) of asim6 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe6 enables/disables transmission 0 disables transmission o peration (synchronously resets the transmission circuit). rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to high level when power6 = 0 during transmission. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. caution clear power6 to 0 after clearing t xe6 and rxe6 to 0 to stop the operation. to start the communication, set power6 to 1, and then set txe6 or rxe6 to 1. remark to use the r x d6/p14 and t x d6/p13 pins as general-purpose port pins, see chapter 5 port functions .
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 364 15.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the cksr6 register (see figure 15-8 ). <2> set the brgc6 register (see figure 15-9 ). <3> set bits 0 to 4 (isrm6, sl6, cl6, ps60, ps61) of the asim6 register (see figure 15-5 ). <4> set bits 0 and 1 (txdlv6, di r6) of the asicl6 register (see figure 15-10 ). <5> set bit 7 (power6) of the asim6 register to 1. <6> set bit 6 (txe6) of the asim6 register to 1. transmission is enabled. set bit 5 (rxe6) of the asim6 register to 1. reception is enabled. <7> write data to transmit buffer register 6 (txb6). data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 15-2. relationship between register settings and pins pin function power6 txe6 rxe6 pm13 p13 pm14 p14 uart6 operation t x d6/p13 r x d6/p14 0 0 0 note note note note stop p13 p14 0 1 note note 1 reception p13 r x d6 1 0 0 1 note note transmission t x d6 p14 1 1 1 0 1 1 transmission/ reception t x d6 r x d6 note can be set as port function. remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm1 : port mode register p1 : port output latch
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 365 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. figure 15-13. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (asim6). whether data is communicated with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is s pecified by bit 0 (txdlv6) of asicl6.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 366 figure 15-14. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 367 (b) parity types and operation the parity bit is used to detect a bit error in communicati on data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 wh en the device is inco rporated in lin. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 368 (c) normal transmission when bit 7 (power6) of asynchronous serial interface o peration mode register 6 (asim6) is set to 1 and bit 6 (txe6) of asim6 is then set to 1, transmission is enabl ed. transmission can be started by writing transmit data to transmit buffer register 6 (txb6 ). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the data in txb6 is transferred to transmit sh ift register 6 (txs6). after that, the transmit data is sequentially output from txs6 to the t x d6 pin. when transmission is completed, the parity and stop bits set by asim6 are appended and a transmission completion interrupt request (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 15-15 shows the timing of the transmission comp letion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 15-15. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 369 (d) continuous transmission the next transmit data can be written to transmit buffer re gister 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, the txb6 register can be e fficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by readi ng bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) when the transmission completion interrupt has occurred. to transmit data continuously, be sure to reference t he asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. cautions 1. the txbf6 and txsf6 flags of the asif6 register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6 a nd txsf6 flags for judgment. read only the txbf6 flag when executing continuous transmission. 2. when the device is incorp orated in a lin, the continuous transmission function cannot be used. make sure that a synchronous serial interface tran smission status register 6 (asif6) is 00h before writin g transmit data to transmit buffer register 6 (txb6). txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transm ission unit upon completion of continuous transmission, be sure to check that the txsf 6 flag is ?0? after generation of the transmission completion interrupt, and then execute initialization. if initialization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. 2. during continuous transmi ssion, the next transmission m ay complete before execution of intst6 interrupt servicing after tran smission of one data frame. as a countermeasure, detection can be performe d by developing a program that can count the number of transmit data and by referencing the txsf6 flag.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 370 figure 15-16 shows an example of the continuous transmission processing flow. figure 15-16. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurs? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag)
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 371 figure 15-17 shows the timing of starting continuous transmission, and figure 15-18 shows the timing of ending continuous transmission. figure 15-17. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which t xbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 372 figure 15-18. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface operation mode register (asim6) txe6: bit 6 of asynchronous serial interface operation mode register (asim6)
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 373 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator st arts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 15-19). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receiv e data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and a recept ion error interrupt (intsr6/intsre 6) is generated on completion of reception. figure 15-19. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. if a reception error occu rs, read asis6 and then rxb6 to clear the error flag. otherwise, an overrun error will occur when the next data is r eceived, and the reception error status will persist. 2. reception is always performed with the ?num ber of stop bits = 1? . the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 6 (asis6) before reading rxb6.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 374 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6 (asis6) is set as a result of data reception, a reception error interrupt r equest (intsr6/intsre6) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis6 in the reception error interrupt (intsr6/intsre6) servicing (see figure 15-6 ). the contents of asis6 are cleared to 0 when asis6 is read. table 15-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). the reception error interrupt can be separated into reception completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynch ronous serial interface operation mode register 6 (asim6) to 0. figure 15-20. reception error interrupt 1. if isrm6 is cleared to 0 (recep tion completion interr upt (intsr6) and error interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 375 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 15- 21, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 15-21. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p14 q in ld_en q (h) sbf transmission when the device is incorporated in li n, the sbf (synchronous break fiel d) transmission control function is used for transmission. for the tr ansmission operation of lin, see figure 15-1 lin transmission operation . when bit 7 (power6) of asynchronous serial interf ace mode register 6 (asim6) is set to 1, the t x d6 pin outputs high level. next, when bit 6 (txe6) of asim6 is set to 1, the transmission e nabled status is entered, and sbf transmission is started by setting bit 5 (sbtt6) of asynchronous serial interface control register 6 (asicl6) to 1. thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (sbl62 to sbl60) of asicl6) is output. following the end of sbf transmission, the transmission completi on interrupt request (i ntst6) is generated and sbtt6 is automatically cleared. thereafter, the normal transmission mode is restored. transmission is suspended until the dat a to be transmitted next is written to transmit buffer register 6 (txb6), or until sbtt6 is set to 1. figure 15-22. sbf transmission t x d6 intst6 sbtt6 1 2 3 4 5 6 7 8 9 10 11 12 13 stop remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request sbtt6: bit 5 of asynchronous serial interface control register 6 (asicl6)
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 376 (i) sbf reception when the device is incorporated in lin, the sbf (synch ronous break field) recept ion control function is used for reception. for the re ception operation of lin, see figure 15-2 lin reception operation . reception is enabled when bit 7 (power6) of asynch ronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is se t to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface contro l register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. w hen the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt reques t (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatical ly cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of as ynchronous serial interface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the width of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been re ceived, and the sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 15-23. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ?0? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 377 15.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 3 to 0 (tps63 to tps60) of clock selectio n register 6 (cksr6) is supplied to each module when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is 1. this clock is called the base clock and its frequency is called f xclk6 . the base clock is fixed to low level when power6 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 agai n when one frame of data has been completely transmitted. if there is no data to be transmitted next, the count er is not cleared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected.
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 378 figure 15-24. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output f xclk6 remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6 (2) generation of serial clock a serial clock to be generated can be specified by usin g clock selection register 6 (cksr6) and baud rate generator control register 6 (brgc6). the clock to be input to the 8-bit counter can be set by bits 3 to 0 (tps63 to tps60) of cksr6 and the division value (f xclk6 /8 to f xclk6 /255) of the 8-bit counter can be set by bits 7 to 0 (mdl67 to mdl60) of brgc6. table 15-4. set value of tps63 to tps60 base clock (f xclk6 ) selection tps63 tps62 tps61 tps60 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs 2 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz 0 1 1 0 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 15.625 khz 39.06 khz 78.13 khz 156.25 khz 1 0 0 0 f prs /2 8 7.813 khz 19.53 khz 39.06 khz 78.13 khz 1 0 0 1 f prs /2 9 3.906 khz 9.77 khz 19.53 khz 39.06 khz 1 0 1 0 f prs /2 10 1.953 khz 4.88 khz 9.77 khz 19.53 khz 1 0 1 1 tm50 output other than above setting prohibited
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 379 (a) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk6 : frequency of base clock selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of br gc6 register (k = 8, 9, 10, ..., 255) (b) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate ra nge during reception. example: frequency of base clock = 10 mhz = 10,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 00100001b (k = 33) target baud rate = 153600 bps baud rate = 10 m/(2 33) = 10000000/(2 33) = 151,515 [bps] error = (151515/153600 ? 1) 100 = ? 1.357 [%] actual baud rate (baud rate with error) desired baud rate (correct baud rate) f xclk6 2 k
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 380 (3) example of setting baud rate table 15-5. set data of baud rate generator f prs = 2.0 mhz f prs = 5.0 mhz f prs = 10.0 mhz f prs = 20.0 mhz baud rate [bps] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] 300 8h 13 301 0.16 7h 65 301 0.16 8h 65 301 0.16 9h 65 301 0.16 600 7h 13 601 0.16 6h 65 601 0.16 7h 65 601 0.16 8h 65 601 0.16 1200 6h 13 1202 0.16 5h 65 1202 0.16 6h 65 1202 0.16 7h 65 1202 0.16 2400 5h 13 2404 0.16 4h 65 2404 0.16 5h 65 2404 0.16 6h 65 2404 0.16 4800 4h 13 4808 0.16 3h 65 4808 0.16 4h 65 4808 0.16 5h 65 4808 0.16 9600 3h 13 9615 0.16 2h 65 9615 0.16 3h 65 9615 0.16 4h 65 9615 0.16 19200 2h 13 19231 0.16 1h 65 19231 0.16 2h 65 19231 0.16 3h 65 19231 0.16 24000 1h 21 23810 ? 0.79 3h 13 24038 0.16 4h 13 24038 0.16 5h 13 24038 0.16 31250 1h 4 31250 0 4h 5 31250 0 5h 5 31250 0 6h 5 31250 0 38400 1h 13 38462 0.16 0h 65 38462 0.16 1h 65 38462 0.16 2h 65 38462 0.16 48000 0h 21 47619 ? 0.79 2h 13 48077 0.16 3h 13 48077 0.16 4h 13 48077 0.16 76800 0h 13 76923 0.16 0h 33 75758 ? 1.36 0h 65 76923 0.16 1h 65 76923 0.16 115200 0h 9 111111 ? 3.55 1h 11 113636 ? 1.36 0h 43 116279 0.94 0h 87 114943 ? 0.22 153600 ? ? ? ? 1h 8 156250 1.73 0h 33 151515 ? 1.36 1h 33 151515 ? 1.36 312500 ? ? ? ? 0h 8 312500 0 1h 8 312500 0 2h 8 312500 0 remark tps63 to tps60: bits 3 to 0 of clock select ion register 6 (cksr6) (setting of base clock (f xclk6 )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 8, 9, 10, ..., 255) f prs : peripheral hardware clock frequency err: baud rate error
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 381 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 15-25. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart6 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 15-25, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 6 (brgc6) a fter the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart6 k: set value of brgc6 fl: 1-bit data length margin of latch timing: 2 clocks
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 382 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 15-6. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the permissible error of reception depends on t he number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 k ? 2 2k 21k + 2 2k
chapter 15 serial interface uart6 preliminary user?s manual u17260ej3v1ud 383 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. howeve r, the result of communica tion is not affected because the timing is initialized on the recepti on side when the start bit is detected. figure 15-26. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 fl + 2/f xclk6
preliminary user?s manual u17260ej3v1ud 384 chapter 16 serial interfaces csi10 and csi11 the pd78f0531, 78f0532, and 78f0533 incorporat e serial interface csi10, and the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d incorporate serial interfaces csi10 and csi11. 16.1 functions of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 have the following two modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial communication is not performed and can enable a reduction in the power consumption. for details, see 16.4.1 operation stop mode . (2) 3-wire serial i/o mode (ms b/lsb-first selectable) this mode is used to communicate 8-bit data using three lines: a serial clock line (sck1n) and two serial data lines (si1n and so1n). the processing time of data communication can be s hortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is communicated with the msb or lsb first can be specified, so this interface can be connected to any device. the 3-wire serial i/o mode is used for connecting periphe ral ics and display controllers with a clocked serial interface. for details, see 16.4.2 3-wire serial i/o mode . remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 385 16.2 configuration of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 include the following hardware. table 16-1. configuration of serial interfaces csi10 and csi11 item configuration controller transmit controller clock start/stop controller & clock phase controller registers transmit buffer register 1n (sotb1n) serial i/o shift re gister 1n (sio1n) control registers serial operation mode register 1n (csim1n) serial clock selection register 1n (csic1n) port mode register 0 (pm0) or port mode register 1 (pm1) port register 0 (p0) or port register 1 (p1) remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d figure 16-1. block diagram of serial interface csi10 internal bus si10/p11/r x d0 intcsi10 f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 sck10/p10/txd0 transmit buffer register 10 (sotb10) transmit controller clock start/stop controller & clock phase controller serial i/o shift register 10 (sio10) output selector so10/p12 output latch 8 transmit data controller 8 output latch (p12) pm12 (a) baud rate generator output latch (p10) pm10 selector remark (a): so10 output
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 386 figure 16-2. block diagram of serial interface csi11 (available only in the pd78f0534, 78f0535, 78f05 36, 78f0537, 78f0537d) 8 8 internal bus output selector output latch transmit controller clock start/stop controller & clock phase controller so11/p02 intcsi11 transmit buffer register 11 (sotb11) transmit data controller si11/p03 serial i/o shift register 11 (sio11) f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 ssi11 output latch (p02) pm02 (a) baud rate generator output latch (p04) pm04 sck11/p04 ssi11 selector remark (a): so11 output (1) transmit buffer register 1n (sotb1n) this register sets the transmit data. transmission/reception is started by wr iting data to sotb1n when bit 7 (csie 1n) and bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. the data written to sotb1n is converted from parallel data into serial data by serial i/o shift register 1n, and output to the serial output pin (so1n). sotb1n can be written or read by an 8- bit memory manipulation instruction. reset signal generation sets this register to 00h. cautions 1. do not access sotb1n when csot1n = 1 (during serial communication). 2. in the slave mode, transmi ssion/reception is started when da ta is written to sotb11 with a low level input to the ssi11 pin. for details on the tran smission/reception operation, see 16.4.2 (2) communication operation. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 387 (2) serial i/o shift register 1n (sio1n) this is an 8-bit register that converts data from parallel data into serial data and vice versa. this register can be read by an 8-bit memory manipulation instruction. reception is started by reading data fr om sio1n if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 0. during reception, the data is read from the serial input pin (si1n) to sio1n. reset signal generation sets this register to 00h. cautions 1. do not access sio1n when cs ot1n = 1 (during serial communication). 2. in the slave mode, reception is started when data is read from sio11 with a low level input to the ssi11 pin. for deta ils on the reception operation, see 16.4.2 (2) communication operation. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 388 16.3 registers controlling seri al interfaces csi10 and csi11 serial interfaces csi10 and csi11 are cont rolled by the following four registers. ? serial operation mode register 1n (csim1n) ? serial clock selection register 1n (csic1n) ? port mode register 0 (pm0) or port mode register 1 (pm1) ? port register 0 (p0) or port register 1 (p1) (1) serial operation mode register 1n (csim1n) csim1n is used to select the operation m ode and enable or disable operation. csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d figure 16-3. format of serial oper ation mode register 10 (csim10) address: ff80h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd10 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 6 first bit specification 0 msb 1 lsb csot10 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. to use p10/sck10/t x d0 and p12/so10 as general-purpose por ts, set csim10 in the default status (00h). 3. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. 4. do not rewrite trmd10 when csot10 = 1 (during serial communication). 5. the so10 output (see (a) in figure 16-1 ) is fixed to the low level when trmd10 is 0. reception is started when data is read from sio10. 6. do not rewrite dir10 when csot10 = 1 (during serial communication). caution be sure to clear bit 5 to 0.
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 389 figure 16-4. format of serial oper ation mode register 11 (csim11) address: ff88h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd11 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode sse11 notes 6, 7 ssi11 pin use selection 0 ssi11 pin is not used 1 ssi11 pin is used dir11 note 8 first bit specification 0 msb 1 lsb csot11 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. to use p02/so11, p04/sck11, and p05/ssi11/ti001 as general-pur pose ports, set csim11 in the default status (00h). 3. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset. 4. do not rewrite trmd11 when csot11 = 1 (during serial communication). 5. the so11 output (see (a) in figure 16-2 ) is fixed to the low level when trmd11 is 0. reception is started when data is read from sio11. 6. do not rewrite sse11 when csot11 = 1 (during serial communication). 7. before setting this bit to 1, fix the ssi11 pin input level to 0 or 1. 8. do not rewrite dir11 when csot11 = 1 (during serial communication).
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 390 (2) serial clock selecti on register 1n (csic1n) this register specifies the timing of the data transmission/reception and sets the serial clock. csic1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d figure 16-5. format of serial clo ck selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 csi10 serial clock selection cks102 cks101 cks100 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz mode 0 0 0 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 1 0 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 1 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 1 0 0 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 7 15.63 khz 39.06 khz 78.13 khz 156.25 khz master mode 1 1 1 external clock input to sck10 slave mode cautions 1. do not write to csic10 while csie10 = 1 (operation enabled). 2. to use p10/sck10/t x d0 and p12/so10 as general-purpose ports, set csic10 in the default status (00h). 3. the phase type of the data clock is type 1 after reset. remark f prs : peripheral hardware clock frequency
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 391 figure 16-6. format of serial clo ck selection register 11 (csic11) address: ff89h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic11 0 0 0 ckp11 dap11 cks112 cks111 cks110 ckp11 dap11 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 4 csi11 serial clock selection cks112 cks111 cks110 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz mode 0 0 0 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 1 0 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 1 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 1 0 0 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 7 15.63 khz 39.06 khz 78.13 khz 156.25 khz master mode 1 1 1 external clock input to sck11 slave mode cautions 1. do not write to csic11 while csie11 = 1 (operation enabled). 2. to use p02/so11 and p04/sck11 as general- purpose ports, set csic11 in the default status (00h). 3. the phase type of the data clock is type 1 after reset. remark f prs : peripheral hardware clock frequency
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 392 (3) port mode registers 0 and 1 (pm0, pm1) these registers set port 0 and 1 input/output in 1-bit units. when using p10/sck10 and p04/sck11 note as the clock output pins of the se rial interface, clear pm10 and pm04 to 0, and set the output latches of p10 and p04 to 1. when using p12/so10 and p02/so11 note as the data output pins of the seri al interface, clear pm12, pm02, and the output latches of p12 and p02 to 0. when using p10/sck10 and p04/sck11 note as the clock input pins of t he serial interface, p11/si10/r x d0 and p03/si11 note as the data input pins, and p05/ssi11 note /ti001 as the chip select input pin, set pm10, pm04, pm11, pm03, and pm05 to 1. at this time, the output latches of p10, p04, p11, p03, and p05 may be 0 or 1. pm0 and pm1 can be set by a 1-bit or 8- bit memory manipulation instruction. reset signal generation sets these registers to ffh. note available only in the pd78f0534, 78f0535, 78f05 36, 78f0537, 78f0537d figure 16-7. format of port mode register 0 (pm0) 7 1 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 6) output mode (output buffer on) input mode (output buffer off) figure 16-8. format of port mode register 1 (pm1) 7 pm17 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 symbol pm1 address: ff21h after reset: ffh r/w pm1n 0 1 p1n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off)
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 393 16.4 operation of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 can be used in the following two modes. ? operation stop mode ? 3-wire serial i/o mode 16.4.1 operation stop mode serial communication is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p10/sck10/t x d0, p11/si10/r x d0, p12/so10, p02/so11 note , p03/si11 note , and p04/sck11 note pins can be used as ordinary i/o port pins in this mode. note available only in the pd78f0534, 78f0535, 78f05 36, 78f0537, 78f0537d (1) register used the operation stop mode is set by serial operation mode register 1n (csim1n). to set the operation stop mode, clear bit 7 (csie1n) of csim1n to 0. (a) serial operation mode register 1n (csim1n) csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets csim1n to 00h. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d ? serial operation mode register 10 (csim10) address: ff80h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use p10/sck10/t x d0 and p12/so10 as general-purpose ports, set csim10 in the default status (00h). 2. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. ? serial operation mode register 11 (csim11) address: ff88h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use p02/so11, p04/sck11, and p05/ssi11/ti001 as general- purpose ports, set csim11 in the default status (00h). 2. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset.
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 394 16.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is used for connecting peripheral ics and display controll ers with a clocked serial interface. in this mode, communication is executed by using three lin es: the serial clock (sck1n), serial output (so1n), and serial input (si1n) lines. (1) registers used ? serial operation mode register 1n (csim1n) ? serial clock selection register 1n (csic1n) ? port mode register 0 (pm0) or port mode register 1 (pm1) ? port register 0 (p0) or port register 1 (p1) the basic procedure of setting an operation in the 3-wire se rial i/o mode is as follows. <1> set the csic1n register (see figures 16-5 and 16-6 ). <2> set bits 0 and 4 to 6 (csot1n, dir1n, sse11 (ser ial interface csi11 only), and trmd1n) of the csim1n register (see figures 16-3 and 16-4 ). <3> set bit 7 (csie1n) of the csim1n register to 1. transmission/reception is enabled. <4> write data to transmit buffer register 1n (sotb1n). data transmission/reception is started. read data from serial i/o shift register 1n (sio1n). data reception is started. caution take relationship with the other party of communication when setting the port mode register and port register. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 395 the relationship between the register settings and pins is shown below. table 16-2. relationship between register settings and pins (1/2) (a) serial interface csi10 pin function csie10 trmd10 pm11 p11 pm12 p12 pm10 p10 csi10 operation si10/r x d0/ p11 so10/p12 sck10/ t x d0/p10 0 note 1 note 1 note 1 note 1 note 1 note 1 stop r x d0/p11 p12 t x d0/ p10 note 2 1 0 1 note 1 note 1 1 slave reception note 3 si10 p12 sck10 (input) note 3 1 1 note 1 note 1 0 0 1 slave transmission note 3 r x d0/p11 so10 sck10 (input) note 3 1 1 1 0 0 1 slave transmission/ reception note 3 si10 so10 sck10 (input) note 3 1 0 1 note 1 note 1 0 1 master reception si10 p12 sck10 (output) 1 1 note 1 note 1 0 0 0 1 master transmission r x d0/p11 so10 sck10 (output) 1 1 1 0 0 0 1 master transmission/ reception si10 so10 sck10 (output) notes 1. can be set as port function. 2. to use p10/sck10/t x d0 as port pins, clear ckp10 to 0. 3. to use the slave mode, set cks102, cks101, and cks100 to 1, 1, 1. remark : don?t care csie10: bit 7 of serial operation mode register 10 (csim10) trmd10: bit 6 of csim10 ckp10: bit 4 of serial clock selection register 10 (csic10) cks102, cks101, cks100: bits 2 to 0 of csic10 pm1 : port mode register p1 : port output latch
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 396 table 16-2. relationship between register settings and pins (2/2) (b) serial interface csi 11 (available only in the pd78f0534, 78f0535, 78f0536, 78f0537, 78f0537d) pin function csie11 trmd11 sse11 pm03 p03 pm02 p02 pm04 p04 pm05 p05 csi11 operation si11/ p03 so11/ p02 sck11/ p04 ssi11/ ti001/p05 0 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 stop p03 p02 p04 note 2 ti001/ p05 0 note 1 note 1 ti001/ p05 1 0 1 1 note 1 note 1 1 1 slave reception note 3 si11 p02 sck11 (input) note 3 ssi11 0 note 1 note 1 ti001/ p05 1 1 1 note 1 note 1 0 0 1 1 slave transmission note 3 p03 so11 sck11 (input) note 3 ssi11 0 note 1 note 1 ti001/ p05 1 1 1 1 0 0 1 1 slave transmission/ reception note 3 si11 so11 sck11 (input) note 3 ssi11 1 0 0 1 note 1 note 1 0 1 note 1 note 1 master reception si11 p02 sck11 (output) ti001/ p05 1 1 0 note 1 note 1 0 0 0 1 note 1 note 1 master transmission p03 so11 sck11 (output) ti001/ p05 1 1 0 1 0 0 0 1 note 1 note 1 master transmission/ reception si11 so11 sck11 (output) ti001/ p05 notes 1. can be set as port function. 2. to use p04/sck11 as port pins, clear ckp11 to 0. 3. to use the slave mode, set cks112, cks111, and cks110 to 1, 1, 1. remark : don?t care csie11: bit 7 of serial operation mode register 11 (csim11) trmd11: bit 6 of csim11 ckp11: bit 4 of serial clock selection register 11 (csic11) cks112, cks111, cks110: bits 2 to 0 of csic11 pm0 : port mode register p0 : port output latch
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 397 (2) communication operation in the 3-wire serial i/o mode, data is tr ansmitted or received in 8-bit units. each bit of the dat a is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. transmission/reception is started when a value is writt en to transmit buffer register 1n (sotb1n). in addition, data can be received when bit 6 (trmd1n) of seri al operation mode register 1n (csim1n) is 0. reception is started when dat a is read from serial i/o shift register 1n (sio1n). however, communication is performed as follows if bit 5 (s se11) of csim11 is 1 when serial interface csi11 is in the slave mode. <1> low level input to the ssi11 pin transmission/reception is started when sotb11 is writt en, or reception is star ted when sio11 is read. <2> high level input to the ssi11 pin transmission/reception or reception is held, therefore, even if sotb11 is written or sio11 is read, transmission/reception or rece ption will not be started. <3> data is written to sotb11 or data is read from sio 11 while a high level is input to the ssi11 pin, then a low level is input to the ssi11 pin transmission/reception or reception is started. <4> a high level is input to the ssi11 pi n during transmission/reception or reception transmission/reception or reception is suspended. after communication has been started, bit 0 (csot1n) of csim1n is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif1n) is set, and csot1n is cleared to 0. then the next communication is enabled. cautions 1. do not access the cont rol register and data register when csot1n = 1 (during serial communication). 2. when using serial interface csi11, wait fo r the duration of at least one clock before the clock operation is started to ch ange the level of the ssi11 pin in the slave mode; otherwise, malfunctioning may occur. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 398 figure 16-9. timing in 3-wire serial i/o mode (1/2) (a) transmission/reception timing (t ype 1: trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 0, sse11 = 1 note ) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb1n. sck1n sotb1n sio1n csot1n csiif1n so1n si1n (receive aah) read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 399 figure 16-9. timing in 3-wire serial i/o mode (2/2) (b) transmission/reception timing (t ype 2: trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 1, sse11 = 1 note ) abh 56h adh 5ah b5h 6ah d5h sck1n sotb1n sio1n csot1n csiif1n so1n si1n (input aah) aah 55h (communication data) 55h is written to sotb1n. read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 400 figure 16-10. timing of clock/data phase (a) type 1: ckp1n = 0, dap1n = 0, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (b) type 2: ckp1n = 0, dap1n = 1, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (c) type 3: ckp1n = 1, dap1n = 0, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (d) type 4: ckp1n = 1, dap1n = 1, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n remarks 1. n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d 2. the above figure illustrates a communication operat ion where data is transmitted with the msb first.
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 401 (3) timing of output to so1n pin (first bit) when communication is started, the value of transmit buffe r register 1n (sotb1n) is output from the so1n pin. the output operation of the first bit at this time is described below. figure 16-11. output operation of first bit (1/2) (a) type 1: ckp1n = 0, dap1n = 0 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit output latch (b) type 3: ckp1n = 1, dap1n = 0 sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n first bit 2nd bit the first bit is directly latched by the sotb1n register to the output latch at the falling (or rising) edge of sck1n, and output from the so1n pin via an output selector. then, the value of the sotb1n regi ster is transferred to the sio1n register at the next rising (or fa lling) edge of sck1n, and shifted one bit. at the same time, the first bit of the receive data is stored in the s io1n register via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the output latch at the next falling (or rising) edge of sck1n, and the data is output from the so1n pin. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 402 figure 16-11. output operation of first bit (2/2) (c) type 2: ckp1n = 0, dap1n = 1 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit 3rd bit output latch (d) type 4: ckp1n = 1, dap1n = 1 first bit 2nd bit 3rd bit sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n the first bit is directly latched by the sotb1n register at the falling edge of the write signal of the sotb1n register or the read signal of the sio1n register, and output from the so1n pin via an output selector. then, the value of the sotb1n register is transfe rred to the sio1n register at the next falling (or rising) edge of sck1n, and shifted one bit. at the same time, the first bit of the rece ive data is stored in the sio1n register via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the out put latch at the next rising (or falling) edge of sck1n, and the data is output from the so1n pin. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 403 (4) output value of so1n pin (last bit) after communication has been completed, the so1n pin holds the output value of the last bit. figure 16-12. output value of so1n pin (last bit) (1/2) (a) type 1: ckp1n = 0, dap1n = 0 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n ( next request is issued.) last bit output latch (b) type 3: ckp1n = 1, dap1n = 0 last bit ( next request is issued.) sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 404 figure 16-12. output value of so1n pin (last bit) (2/2) (c) type 2: ckp1n = 0, dap1n = 1 sck1n sotb1n sio1n so1n last bit writing to sotb1n or reading from sio1n ( next request is issued.) output latch (d) type 4: ckp1n = 1, dap1n = 1 last bit ( next request is issued.) sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u17260ej3v1ud 405 (5) so1n output (see (a) in figures 16-1 and 16-2) the status of the so1n output is as follows if bit 7 (csie1n) of seri al operation mode register 1n (csim1n) is cleared to 0. table 16-3. so1n output status trmd1n dap1n dir1n so1n output note 1 trmd1n = 0 note 2 ? ? outputs low level note 2 dap1n = 0 ? value of so1n latch (low-level output) dir1n = 0 value of bit 7 of sotb1n trmd1n = 1 dap1n = 1 dir1n = 1 value of bit 0 of sotb1n notes 1. the actual output of the so 10/p12 or so11/p02 pin is determined according to pm12 and p12 or pm02 and p02, as well as the so1n output. 2. status after reset caution if a value is written to trmd1n, dap1n, and dir1n, the output value of so1n changes. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
preliminary user?s manual u17260ej3v1ud 406 chapter 17 serial interface iic0 17.1 functions of serial interface iic0 serial interface iic0 has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. this mode complies with the i 2 c bus format and the master device can generated ?start condition?, ?address?, ?transfer direction specification?, ?dat a?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects these received status and data by har dware. this function can simplify the part of application prog ram that controls the i 2 c bus. since the scl0 and sda0 pins are used for open drain ou tputs, iic0 requires pull-up resistors for the serial clock line and the serial data bus line. figure 17-1 shows a block diagram of serial interface iic0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 407 figure 17-1. block diagram of serial interface iic0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator bus status detector match signal iic shift register 0 (iic0) so latch iice0 dq set clear cl01, cl00 trc0 dfc0 dfc0 sda0/ p61 scl0/ p60 data hold time correction circuit start condition generator stop condition generator ack generator wake-up controller ack detector output control stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic0 iic shift register 0 (iic0) iicc0.stt0, spt0 iics0.msts0, exc0, coi0 iics0.msts0, exc0, coi0 f prs lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detector internal bus cld0 dad0 smc0 dfc0 cl01 cl00 clx0 iic clock selection register 0 (iiccl0) stcf iicbsy stcen iicrsv iic flag register 0 (iicf0) iic function expansion register 0 (iicx0) n-ch open- drain output pm61 output latch (p61) n-ch open- drain output pm60 output latch (p60) exscl0/ p62
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 408 figure 17-2 shows a serial bus configuration example. figure 17-2. serial bus c onfiguration example using i 2 c bus master cpu1 slave cpu1 address 0 sda0 scl0 serial data bus serial clock + v dd + v dd sda0 scl0 sda0 scl0 sda0 scl0 sda0 scl0 master cpu2 slave cpu2 address 1 slave cpu3 address 2 slave ic address 3 slave ic address n
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 409 17.2 configuration of serial interface iic0 serial interface iic0 includes the following hardware. table 17-1. configuration of serial interface iic0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iicf0) iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) port mode register 6 (pm6) port register 6 (p6) (1) iic shift register 0 (iic0) iic0 is used to convert 8-bit serial data to 8-bit paralle l data and vice versa in synchronization with the serial clock. iic0 can be used for both transmission and reception. the actual transmit and receive operations can be contro lled by writing and reading operations to iic0. cancel the wait state and start data transfer by writing data to iic0 during the wait period. iic0 is set by an 8-bit memory manipulation instruction. reset signal generati on sets iic0 to 00h. figure 17-3. format of iic shift register 0 (iic0) symbol iic0 address: ffa5h after reset: 00h r/w 76543210 cautions 1. do not write data to iic0 during data transfer. 2. write or read iic0 only during the wait period. accessing iic0 in a communication state other than during the wait period is prohibit ed. when the device serves as the master, however, iic0 can be written only once after the communication trigger bit (stt0) is set to 1. (2) slave address register 0 (sva0) this register stores local addresses when in slave mode. sva0 is set by an 8-bit memory manipulation instruction. however, rewriting to this register is prohibited wh ile std0 = 1 (while the start condition is detected). reset signal generation sets sva0 to 00h. figure 17-4. format of slave address register 0 (sva0) symbol sva0 address: ffa7h after reset: 00h r/w 76543210 0 note note bit 0 is fixed to 0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 410 (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wake-up controller this circuit generates an interrupt request (intiic0) w hen the address received by this register matches the address value set to slave address register 0 (sva0) or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output or input during transmi t/receive operations and is used to verify that 8-bit data was transmitted or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt request is generated by the following two triggers. falling edge of eighth or ninth clock of the serial clock (set by wtim0 bit) interrupt request generated when a stop cond ition is detected (set by spie0 bit) remark wtim0 bit: bit 3 of iic control register 0 (iicc0) spie0 bit: bit 4 of iic control register 0 (iicc0) (8) serial clock controller in master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits generate and detect each status. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start conditi on when the stt0 bit is set to 1. however, in the communication reservation disabled stat us (iicrsv bit = 1), when the bus is not released (iicbsy bit = 1), start condition requests are ignored and the stcf bit is set to 1. (13) stop condition generator this circuit generates a stop condition when the spt0 bit is set to 1.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 411 (14) bus status detector this circuit detects whether or not the bus is releas ed by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediately following operation, the initial status is set by the stcen bit. remark stt0 bit: bit 1 of iic control register 0 (iicc0) spt0 bit: bit 0 of iic control register 0 (iicc0) iicrsv bit: bit 0 of iic flag register 0 iicbsy bit: bit 6 of iic flag register 0 stcf bit: bit 7 of iic flag register 0 stcen bit: bit 1 of iic flag register 0
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 412 17.3 registers to control serial interface iic0 serial interface iic0 is controlled by the following seven registers. iic control register 0 (iicc0) iic flag register 0 (iicf0) iic status register 0 (iics0) iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) port mode register 6 (pm6) port register 6 (p6) (1) iic control register 0 (iicc0) this register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. iicc0 is set by a 1-bit or 8-bit memory manipulation in struction. however, set the spie0, wtim0, and acke0 bits while iice0 bit = 0 or during the wait period. thes e bits can be set at the same time when the iice0 bit is set from ?0? to ?1?. reset signal generation sets iicc0 to 00h.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 413 figure 17-5. format of iic control register 0 (iicc0) (1/4) address: ffa6h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c operation enable 0 stop operation. reset iic status register 0 (iics0) note 1 . stop internal operation. 1 enable operation. be sure to set this bit (1) while the scl0 and sda0 lines are at high level. condition for clearing (iice0 = 0) condition for setting (iice0 = 1) ? cleared by instruction ? reset ? set by instruction lrel0 note 2 exit from communications 0 normal operation 1 this exits from the current communications and sets sta ndby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines are set to high impedance. the following flags of iic control register 0 (iicc0) and iic status register 0 (iics0) are cleared to 0. stt0 spt0 msts0 exc0 coi0 trc0 ackd0 std0 the standby mode following exit from communications remains in effect until the following co mmunications en try conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rece ption occurs after the start condition. condition for clearing (lrel0 = 0) condition for setting (lrel0 = 1) ? automatically cleared after execution ? reset ? set by instruction wrel0 note 2 wait cancellation 0 do not cancel wait 1 cancel wait. this setting is automatic ally cleared after wait is canceled. when wrel0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (trc0 = 1), the sda0 line goes into the high impedance state (trc0 = 0). condition for clearing (wrel0 = 0) condition for setting (wrel0 = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics0 register, the stcf0 and iic bsy bits of the iicf0 register, and the cld0 and dad0 bits of the iiccl0 register are reset. 2. this flag?s signal is invalid when iice0 = 0. caution the start condition is detected immediately after i 2 c is enabled to operate (iice0 = 1) while the scl0 line is at high level and the sda0 line is at low level. imme diately after enabling i 2 c to operate (iice0 = 1), set lrel0 (1) by usin g a 1-bit memory manipulation instruction.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 414 figure 17-5. format of iic control register 0 (iicc0) (2/4) spie0 note 1 enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 = 0) condition for setting (spie0 = 1) ? cleared by instruction ? reset ? set by instruction wtim0 note 1 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, cloc k output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this b it. the setting of this bit is valid when the address transfer is comp leted. when in master mode, a wait is inserted at the fallin g edge of the ninth clock during address transfers. for a slave devi ce that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ack) is issued. however, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 = 0) condition for setting (wtim0 = 1) ? cleared by instruction ? reset ? set by instruction acke0 notes 1, 2 acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during the nint h clock period, the sda0 line is set to low level. however, ack is invalid during address transfers and other than in expansion mode. condition for clearing (acke0 = 0) condition for setting (acke0 = 1) ? cleared by instruction ? reset ? set by instruction notes 1. this flag?s signal is invalid when iice0 = 0. 2. the set value is invalid during address transfer and if the code is not an extension code. when the device serves as a slave and the addresses match, an acknowledge is generated regardless of the set value.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 415 figure 17-5. format of iic control register 0 (iicc0) (3/4) stt0 note start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). when the scl0 line is high level, the sda0 line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scl0 is changed to low level. when a third party is communicating: ? when communication reservation function is enabled (iicrsv = 0) functions as the start condition reservation flag. w hen set to 1, automatically generates a start condition after the bus is released. ? when communication reservation function is disabled (iicrsv = 1) stcf is set to 1 and information that is set (1) to stt0 is cleared. no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke0 has been cleared to 0 and slave has been notified of final reception. ? for master transmission: a start condition cannot be genera ted normally during the acknowledge period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as spt0. ? setting stt0 to 1 and then setting it again bef ore it is cleared to 0 is prohibited. condition for clearing (stt0 = 0) condition for setting (stt0 = 1) ? cleared by setting sst0 to 1 while communication reservation is prohibited. ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? cleared by lrel0 = 1 (exit from communications) ? when iice0 = 0 (operation stop) ? reset ? set by instruction note this flag?s signal is invalid when iice0 = 0. remarks 1. bit 1 (stt0) becomes 0 when it is read after data setting. 2. iicrsv: bit 0 of iic flag register (iicf0) stcf: bit 7 of iic flag register (iicf0)
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 416 figure 17-5. format of iic control register 0 (iicc0) (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0 line goes to low level, either set the scl0 li ne to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sda0 line changes from low level to high level and a stop condition is generated. cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke0 has been cleared to 0 and slave has been notified of final reception. ? for master transmission: a stop condition cannot be generat ed normally during the acknowledge period. therefore, set it during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as stt0. ? spt0 can be set to 1 only when in master mode note . ? when wtim0 has been cleared to 0, if spt0 is set to 1 during t he wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. wtim0 should be changed from 0 to 1 during the wait period following the output of eight clocks, and spt0 shoul d be set to 1 during the wait period that follows the outpu t of the ninth clock. ? setting spt0 to 1 and then setting it again bef ore it is cleared to 0 is prohibited. condition for clearing (spt0 = 0) condition for setting (spt0 = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 = 0 (operation stop) ? reset ? set by instruction note set spt0 to 1 only in master mode. however, spt0 mu st be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 17.5.15 other cautions . caution when bit 3 (trc0) of iic status register 0 (iic s0) is set to 1, wrel0 is set to 1 during the ninth clock and wait is canceled, after which trc0 is cleared and the sda0 line is set to high impedance. remark bit 0 (spt0) becomes 0 when it is read after data setting.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 417 (2) iic status register 0 (iics0) this register indicates the status of i 2 c. iics0 is read by a 1-bit or 8-bit memory manipulation instruction only when stt0 = 1 and during the wait period. reset signal generation sets iics0 to 00h. caution if data is read from iics0 , a wait cycle is generated. do not read data from iics0 when the cpu is operating on the subsystem clock and th e peripheral hardware cl ock is stopped. for details, see chapter 31 cautions for wait. figure 17-6. format of iic status register 0 (iics0) (1/3) address: ffaah after reset: 00h r symbol <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 = 0) condition for setting (msts0 = 1) ? when a stop condition is detected ? when ald0 = 1 (arbitration loss) ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald0 detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. msts0 is cleared. condition for clearing (ald0 = 0) condition for setting (ald0 = 1) ? automatically cleared after iics0 is read note ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 = 0) condition for setting (exc0 = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than iics0. therefore, when using the ald0 bit, read the data of this bit before the data of the other bits. remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 418 figure 17-6. format of iic status register 0 (iics0) (2/3) coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 = 0) condition for setting (coi0 = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the received address matches the local address (slave address register 0 (sva0)) (set at the rising edge of the eighth clock). trc0 detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set for high impedance. 1 transmit status. the value in the so0 latch is ena bled for output to the sda0 line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trc0 = 0) condition for setting (trc0 = 1) ? when a stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? cleared by wrel0 = 1 note (wait cancel) ? when ald0 changes from 0 to 1 (arbitration loss) ? reset ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) ? when a start condition is detected ? when ?0? is input to the first byte?s lsb (transfer direction specification bit) ? when a start condition is generated ? when ?0? is output to the first byte?s lsb (transfer direction specification bit) ? when ?1? is input to the first byte?s lsb (transfer direction specification bit) note if the wait status is canceled by setting bit 5 (wrel0) of iic control register 0 (iicc0) to 1 at the ninth clock when bit 3 (trc0) of iic status register 0 ( iics0) is 1, trc0 is cleared, and the sda0 line goes into a high-impedance state. remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 419 figure 17-6. format of iic status register 0 (iics0) (3/3) ackd0 detection of acknowledge (ack) 0 acknowledge was not detected. 1 acknowledge was detected. condition for clearing (ackd0 = 0) condition for setting (ackd0 = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? after the sda0 line is set to low level at the rising edge of scl0?s ninth clock std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std0 = 0) condition for setting (std0 = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s co mmunication is terminated and the bus is released. condition for clearing (spd0 = 0) condition for setting (spd0 = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) (3) iic flag register 0 (iicf0) this register sets the operation mode of i 2 c and indicates the status of the i 2 c bus. iicf0 is set by a 1-bit or 8-bit memory manipulation instruction. however, t he stcf and iicbsy bits are read- only. the iicrsv bit can be used to enable/disable the communication reservation function (see 17.5.14 communication reservation ). stcen can be used to set the in itial value of the iicbsy bit (see 17.5.15 other cautions ). iicrsv and stcen can be written only when the operation of i 2 c is disabled (bit 7 (iice0) of iic control register 0 (iicc0) = 0). when operation is enabled, the iicf0 register can be read. reset signal generation sets iicf0 to 00h.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 420 figure 17-7. format of iic flag register 0 (iicf0) <7> stcf condition for clearing (stcf = 0) ? cleared by stt0 = 1 ? when iice0 = 0 (operation stop) ? reset condition for setting (stcf = 1) ? generating start condition unsuccessful and stt0 cleared to 0 when communication reservation is disabled (iicrsv = 1). stcf 0 1 generate start condition start condition generation unsuccessful: clear stt0 flag stt0 clear flag iicf0 symbol <6> iicbsy 5 0 4 0 3 0 2 0 <1> stcen <0> iicrsv address: ffabh after reset: 00h r/w note condition for clearing (iicbsy = 0) ? detection of stop condition ? when iice0 = 0 (operation stop) ? reset condition for setting (iicbsy = 1) ? detection of start condition ? setting of iice0 when stcen = 0 iicbsy 0 1 bus release status (communication initial status when stcen0 = 1) bus communication status (communication initial status when stcen0 = 0) i 2 c bus status flag condition for clearing (stcen = 0) ? detection of stop condition ? reset condition for setting (stcen = 1) ? set by instruction stcen 0 1 after operation is enabled (iice0 = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice0 = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv = 0) ? cleared by instruction ? reset condition for setting (iicrsv = 1) ? set by instruction iicrsv 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only. cautions 1. write to stcen only when the operation is stopped (iice0 = 0). 2. as the bus release status (iicbsy = 0) is recognized regardless of the actual bus status when stcen = 1, when generating th e first start condition (stt0 = 1), it is necessary to verify that no third party comm unications are in progress in order to prevent such communications from being destroyed. 3. write to iicrsv only when the operation is stopped (iice0 = 0). remark stt0: bit 1 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 421 (4) iic clock selection register 0 (iiccl0) this register is used to set the transfer clock for the i 2 c bus. iiccl0 is set by a 1-bit or 8-bit memory manipulation in struction. however, the cld0 and dad0 bits are read- only. the smc0, cl01, and cl00 bits are set in comb ination with bit 0 (clx0) of iic function expansion register 0 (iicx0) (see 17.3 (6) i 2 c transfer clock setting method ). set iiccl0 while bit 7 (iice0) of iic control register 0 (iicc0) is 0. reset signal generation sets iiccl0 to 00h. figure 17-8. format of iic clock selection register 0 (iiccl0) address: ffa8h after reset: 00h r/w note symbol 7 6 <5> <4> <3> <2> 1 0 iiccl0 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 cld0 detection of scl0 pin level (valid only when iice0 = 1) 0 the scl0 pin was detected at low level. 1 the scl0 pin was detected at high level. condition for clearing (cld0 = 0) condition for setting (cld0 = 1) ? when the scl0 pin is at low level ? when iice0 = 0 (operation stop) ? reset ? when the scl0 pin is at high level dad0 detection of sda0 pin level (valid only when iice0 = 1) 0 the sda0 pin was detected at low level. 1 the sda0 pin was detected at high level. condition for clearing (dad0 = 0) condition for setting (dad0 = 1) ? when the sda0 pin is at low level ? when iice0 = 0 (operation stop) ? reset ? when the sda0 pin is at high level smc0 operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfc0 digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not va ry regardless of dfc0 bit set (1)/clear (0). the digital filter is used for noise elimination in high-speed mode. note bits 4 and 5 are read-only. remark iice0: bit 7 of iic control register 0 (iicc0)
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 422 (5) iic function expansi on register 0 (iicx0) this register sets the function expansion of i 2 c. iicx0 is set by a 1-bit or 8-bit memory manipulation instru ction. the clx0 bit is set in combination with bits 3, 1, and 0 (smc0, cl01, and cl00) of iic cl ock selection register 0 (iiccl0) (see 17.3 (6) i 2 c transfer clock setting method ). set iicx0 while bit 7 (iice0) of iic control register 0 (iicc0) is 0. reset signal generation sets iicx0 to 00h. figure 17-9. format of iic functi on expansion register 0 (iicx0) address: ffa9h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> iicx0 0 0 0 0 0 0 0 clx0 (6) i 2 c transfer clock setting method the i 2 c transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 12, 18, 24, 44, 66, 86 (see table 17-2 selection clock setting ) t: 1/f w t r : scl0 rise time t f : scl0 fall time
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 423 for example, the i 2 c transfer clock frequency (f scl ) when f w = f prs /2 = 4.19 mhz, m = 86, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(88 238.7 ns + 200 ns + 50 ns) ? 48.1 khz m t + t r + t f m/2 t m/2 t t f t r scl0 scl0 inversion scl0 inversion scl0 inversion the selection clock is set using a combination of bits 3, 1, and 0 (smc0, cl01, and cl00) of iic clock selection register 0 (iiccl0) and bit 0 (clx0) of iic function expansion register 0 (iicx0). table 17-2. selection clock setting iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock (f w ) transfer clock (f w /m) settable selection clock (f w ) range operation mode 0 0 0 0 f prs /2 f w /44 2.00 to 4.19 mhz 0 0 0 1 f prs /2 f w /86 0 0 1 0 f prs /4 f w /86 4.19 to 8.38 mhz 0 0 1 1 f exscl0 f w /66 6.4 mhz normal mode (smc0 bit = 0) 0 1 0 f prs /2 f w /24 0 1 1 0 f prs /4 f w /24 4.00 to 8.38 mhz 0 1 1 1 f exscl0 f w /18 6.4 mhz high-speed mode (smc0 bit = 1) 1 0 setting prohibited 1 1 0 f prs /2 f w /12 1 1 1 0 f prs /4 f w /12 4.00 to 4.19 mhz high-speed mode (smc0 bit = 1) 1 1 1 1 setting prohibited caution determine the transf er clock frequency of i 2 c by using clx0, smc0, cl01, and cl00 before enabling the operation (by setting bit 7 (iice0) of iic control register 0 (iicc0) to 1). to change the transfer clock frequency, clear iice0 once to 0. remarks 1. : don?t care 2 . f prs : peripheral hardware clock frequency 3 . f exscl0 : external clock frequency from exscl0 pin
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 424 (7) port mode register 6 (pm6) this register sets the input/output of port 6 in 1-bit units. when using the p60/scl0 pin as clock i/o and the p61/ sda0 pin as serial data i/o, clear pm60 and pm61, and the output latches of p60 and p61 to 0. set iice0 (bit 7 of iic control register 0 (iicc0)) to 1 before setting the output mode because the p60/scl0 and p61/sda0 pins output a low level (fixed) when iice0 is 0. pm6 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generati on sets pm6 to ffh. figure 17-10. format of port mode register 6 (pm6) pm60 pm61 pm62 pm63 1 1 1 1 p6n pin i/o mode selection (n = 0 to 3) output mode (output buffer on) input mode (output buffer off) pm6n 0 1 0 1 2 3 4 5 6 7 pm6 address: ff26h after reset: ffh r/w symbol
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 425 17.4 i 2 c bus mode functions 17.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. (1) scl0 ...... this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. (2) sda0 ...... this pin is used fo r serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drai n outputs, an external pull-up resistor is required. figure 17-11. pin configuration diagram master device clock output (clock input) data output data input v ss v ss scl0 sda0 v dd v dd (clock output) clock input data output data input v ss v ss slave device scl0 sda0
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 426 17.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. figure 17-12 shows the transfer timing for the ?start conditi on?, ?address?, ?data?, and ?st op condition? output via the i 2 c bus?s serial data bus. figure 17-12. i 2 c bus serial data transfer timing scl0 sda0 start condition address r/w ack data 1-7 8 9 1-8 ack data ack stop condition 9 1-8 9 the master device generates the start c ondition, slave address, and stop condition. the acknowledge (ack) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. howeve r, in the slave device, the scl0?s low level period can be extended and a wait can be inserted. 17.5.1 start conditions a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signal s that the master device gener ates to the slave device when starting a serial transfer. when the device is us ed as a slave, start conditions can be detected. figure 17-13. start conditions scl0 sda0 h a start condition is output when bit 1 (stt0) of iic control r egister 0 (iicc0) is set (to 1) after a stop condition has been detected (spd0: bit 0 = 1 in iic status register 0 (iic s0)). when a start condition is detected, bit 1 (std0) of iics0 is set (to 1).
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 427 17.5.2 addresses the address is defined by the 7 bits of data that follow the start condition. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via the bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware t hat detects the start condition and c hecks whether or not the 7-bit address data matches the data values stored in slave address register 0 (sva0). if the address data matches the sva0 values, the slave device is selected and communicates with the master device until th e master device generates a start condition or stop condition. figure 17-14. address scl0 sda0 intiic0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w address note note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. the slave address and the eighth bit, which spec ifies the transfer direction as described in 17.5.3 transfer direction specification below, are together written to iic shift r egister 0 (iic0) and are then output. received addresses are written to iic0. the slave address is assigned to the higher 7 bits of iic0. 17.5.3 transfer di rection specification in addition to the 7-bit address data, the master device s ends 1 bit that specifies t he transfer direction. when this transfer direction specificati on bit has a value of ?0?, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of ?1?, it indicates that the master device is receiving data from a slave device. figure 17-15. transfer direction specification scl0 sda0 intiic0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note note intiic0 is not issued if data other than a local address or extension code is received during slave device operation.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 428 17.5.4 acknowledge (ack) ack is used to check the status of serial data at the transmission and reception sides. the reception side returns ack each time it has received 8-bit data. the transmission side usually receives ack after transmitting 8-bit data. when ack is returned from the reception side, it is assumed that reception has been correctly performed and processi ng is continued. whether ack has been detected can be checked by using bit 2 (ack d0) of iic status register 0 (iics0). when the master receives the last dat a item, it does not return ack and instead generates a stop condition. if a slave does not return ack after receiving data, the ma ster outputs a stop condition or restart condition and stops transmission. if ack is not returned, the possible causes are as follows. <1> reception was not performed normally. <2> the final data item was received. <3> the reception side specified by the address does not exist. to generate ack, the reception side makes the sda0 line low at the ninth clock (indicating normal reception). automatic generation of ack is enabled by setting bit 2 (ac ke0) of iic control register 0 (iicc0) to 1. bit 3 (trc0) of the iics0 register is set by the data of the eighth bit that follows 7-bit addre ss information. usually, set acke0 to 1 for reception (trc0 = 0). if a slave can receive no more data during reception (trc 0 = 0) or does not require the next data item, then the slave must inform the master, by clearing acke0 to 0, that it will not receive any more data. when the master does not require the next data item during reception (trc0 = 0), it must clear acke0 to 0 so that ack is not generated. in this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). figure 17-16. ack scl0 sda0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w ack when the local address is received, ac k is automatically generated, regardl ess of the value of acke0. when an address other than that of t he local address is received, ack is not generated (nack). when an extension code is received, ack is gen erated if acke0 is set to 1 in advance. how ack is generated when data is received differs as follows depending on the setting of the wait timing. ? when 8-clock wait state is selected (b it 3 (wtim0) of iicc0 register = 0): by setting acke0 to 1 before releasing the wait state, ack is generated at the falling edge of the eighth clock of the scl0 pin. ? when 9-clock wait state is selected (b it 3 (wtim0) of iicc0 register = 1): ack is generated by setting acke0 to 1 in advance.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 429 17.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. when the device is used as a slave, stop conditions can be detected. figure 17-17. stop condition scl0 sda0 h a stop condition is generated when bit 0 (spt0) of iic c ontrol register 0 (iicc0) is set to 1. when the stop condition is detected, bit 0 (spd0) of iic status register 0 (iics0) is se t to 1 and intiic0 is generated when bit 4 (spie0) of iicc0 is set to 1.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 430 17.5.6 wait the wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifi es the communication partner of the wait state. when wait state has been canceled for both the master and slave devices, the next data transfer can begin. figure 17-18. wait (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and acke0 = 1) master iic0 scl0 slave iic0 scl0 acke0 transfer lines scl0 sda0 6789 123 master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock iic0 data write (cancel wait) wait after output of eighth clock wait from slave wait from master ffh is written to iic0 or wrel0 is set to 1 678 9 123 d2 d1 d0 d7 d6 d5 ack h
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 431 figure 17-18. wait (2/2) (2) when master and slave devices both have a nine-clock wait (master transmits, slave receives, and acke0 = 1) master iic0 scl0 slave iic0 scl0 acke0 transfer lines scl0 sda0 h 6789 1 23 master and slave both wait after output of ninth clock wait from master and slave wait from slave iic0 data write (cancel wait) ffh is written to iic0 or wrel0 is set to 1 6789 123 d2 d1 d0 ack d7 d6 d5 generate according to previously set acke0 value remark acke0: bit 2 of iic control register 0 (iicc0) wrel0: bit 5 of iic control register 0 (iicc0) a wait may be automatically generated depending on the setting of bit 3 (wtim0) of iic control register 0 (iicc0). normally, the receiving side cancels the wait state when bit 5 (wrel0) of iicc0 is set to 1 or when ffh is written to iic shift register 0 (iic0), and the transmitting side cancels the wait state when data is written to iic0. the master device can also cancel the wait state via either of the following methods. by setting bit 1 (stt0) of iicc0 to 1 by setting bit 0 (spt0) of iicc0 to 1
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 432 17.5.7 canceling wait the i 2 c usually cancels a wait stat e by the following processing. ? writing data to iic shift register 0 (iic0) ? setting bit 5 (wrel0) of iic control register 0 (iicc0) (canceling wait) ? setting bit 1 (stt0) of iic0 register (generating start condition) note ? setting bit 0 (spt0) of iic0 regi ster (generating stop condition) note note master only when the above wait canceling pr ocessing is executed, the i 2 c cancels the wait state and communication is resumed. to cancel a wait state and transmit data (incl uding addresses), write the data to iic0. to receive data after canceling a wait state, or to comple te data transmission, set bit 5 (wrel0) of the iic0 control register 0 (iicc0) to 1. to generate a restart condition after canceling a wait state, set bit 1 (stt0) of iicc0 to 1. to generate a stop condition after canceling a wait state, set bit 0 (spt0) of iicc0 to 1. execute the canceling processing only once for one wait state. if, for example, data is written to iic0 after canceling a wa it state by setting wrel0 to 1, an incorrect value may be output to sda0 because the timing for changing the sd a0 line conflicts with the timing for writing iic0. in addition to the above, communication is stopped if iic e0 is cleared to 0 when communication has been aborted, so that the wait st ate can be canceled. if the i 2 c bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (lrel0) of iicc0, so that the wait state can be canceled. 17.5.8 interrupt request (intiic0) generation timing and wait control the setting of bit 3 (wtim0) of iic c ontrol register 0 (iicc0) determines t he timing by which intiic0 is generated and the corresponding wait control, as shown in table 17-3. table 17-3. intiic0 generation timing and wait control during slave device operation during master device operation wtim0 address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic0 signal and wait period occu rs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (sva0). at this point, ack is generated r egardless of the value set to iicc0?s bit 2 (acke0). for a slave device that has received an extension code, intiic0 occu rs at the falling edge of the eighth clock. however, if the address does not match after rest art, intiic0 is generated at the falling edge of the 9th clock, but wait does not occur. 2. if the received address does not match the contents of slave address register 0 (sva0) and extension code is not received, neither intiic0 nor a wait occurs. remark the numbers in the table indicate the number of t he serial clock?s clock signals. interrupt requests and wait control are both synchronized with t he falling edge of these clock signals.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 433 (1) during address transmission/reception slave device operation: interrupt and wait timi ng are determined depending on the conditions described in notes 1 and 2 above, regardless of the wtim0 bit. master device operation: interrupt and wait timing oc cur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? writing data to iic shift register 0 (iic0) ? setting bit 5 (wrel0) of iic control register 0 (iicc0) (canceling wait) ? setting bit 1 (stt0) of iic0 register (generating start condition) note ? setting bit 0 (spt0) of iic0 regi ster (generating stop condition) note note master only. when an 8-clock wait has been selected (wtim0 = 0) , the presence/absence of ack generation must be determined prior to wait cancellation. (5) stop condition detection intiic0 is generated when a stop condit ion is detected (only when spie0 = 1). 17.5.9 address match detection method in i 2 c bus mode, the master device can se lect a particular slave device by transmitting the corresponding slave address. address match can be detected automatical ly by hardware. an interrupt r equest (intiic0) occurs when a local address has been set to slave address register 0 (sva0) and when the address set to sva0 matches the slave address sent by the master device, or when an extension code has been received. 17.5.10 error detection in i 2 c bus mode, the status of t he serial data bus (sda0) during data transmi ssion is captured by iic shift register 0 (iic0) of the transmitting device, so the iic0 data prior to transmission can be compared with the transmitted iic0 data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 434 17.5.11 extension code (1) when the higher 4 bits of the receive address are ei ther ?0000? or ?1111?, the extension code reception flag (exc0) is set to 1 for extension code reception and an interrupt request (intiic0) is issued at the falling edge of the eighth clock. the local address stored in slave address register 0 (sva0) is not affected. (2) if ?11110 0? is set to sva0 by a 10-bit address transfer and ?11110 0? is transferred from the master device, the results are as follows. note that intiic0 occurs at the falling edge of the eighth clock. higher four bits of data match: exc0 = 1 seven bits of data match: coi0 = 1 remark exc0: bit 5 of iic status register 0 (iics0) coi0: bit 4 of iic status register 0 (iics0) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. if the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. for example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (lrel0) of the iic control register 0 (iicc0) to 1 to set the standby mode for the next communication operation. table 17-4. extension code bit definitions slave address r/w bit description 0 0 0 0 0 0 0 0 general call address 0 0 0 0 0 0 0 1 start byte 0 0 0 0 0 0 1 c-bus address 0 0 0 0 0 1 0 address that is reserved for different bus format 1 1 1 1 0 x x 10-bit slave address specification
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 435 17.5.12 arbitration when several master devices simultaneously generate a star t condition (when stt0 is set to 1 before std0 is set to 1), communication among the master devices is perform ed as the number of clocks are adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (ald 0) in iic status register 0 (iics0) is set (1) via the timing by which the arbitration loss oc curred, and the scl0 and sda0 lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on the timing of the next interrupt reques t (the eighth or ninth clock, when a stop condition is detected, et c.) and the ald0 = 1 setting that has been made by software. for details of interrupt request timing, see 17.5.17 timing of i 2 c interrupt request (intiic0) occurrence . remark std0: bit 1 of iic status register 0 (iics0) stt0: bit 1 of iic control register 0 (iicc0) figure 17-19. arbitration timing example scl0 sda0 scl0 sda0 scl0 sda0 hi-z hi-z master 1 loses arbitration master 1 master 2 transfer lines
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 436 table 17-5. status during arbitrati on and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data transmission when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transf er when stop condition is generated (when spie0 = 1) note 2 when data is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spie0 = 1) note 2 when data is at low level while attempting to generate a stop condition when scl0 is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when wtim0 (bit 3 of iic control register 0 (iicc0 )) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim0 = 0 and the extension code?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a chance that ar bitration will occur, set spie0 = 1 for master device operation. remark spie0: bit 4 of iic control register 0 (iicc0) 17.5.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request si gnal (intiic0) when a local address and extension code have been received. this function makes processing more efficient by pr eventing unnecessary intiic0 signal from occurring when addresses do not match. when a start condition is detected, wake up standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the possibility that an ar bitration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detecte d, bit 4 (spie0) of iic control register 0 (iicc0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 437 17.5.14 communication reservation (1) when communication reservation func tion is enabled (bit 0 (iicrsv) of iic flag register 0 (iicf0) = 0) to start master device communications when not curr ently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. when arbitration results in neither master nor slave operation when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iic control register 0 (iicc0) was set to 1). if bit 1 (stt0) of iicc0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. if an address is written to iic shift register 0 (iic0) afte r bit 4 (spie0) of iicc0 was set to 1, and it was detected by generation of an interrupt request signal (intiic0) that the bus was released (detection of the stop condition), then the device automatically starts communi cation as the master. data written to iic0 before the stop condition is det ected is invalid. when stt0 has been set to 1, the operation mode (as st art condition or as communication reservation) is determined according to the bus status. if the bus has been released .........................................a start c ondition is generated if the bus has not been released (stand by mode) .........communica tion reservation check whether the communication reservation operates or not by using msts0 (bit 7 of iic status register 0 (iics0)) after stt0 is set to 1 and the wait time elapses. the wait periods, which should be set via software, are listed in table 17-6. table 17-6. wait periods clx0 smc0 cl01 cl00 wait period 0 0 0 0 46 clocks 0 0 0 1 86 clocks 0 0 1 0 172 clocks 0 0 1 1 34 clocks 0 1 0 0 0 1 0 1 30 clocks 0 1 1 0 60 clocks 0 1 1 1 12 clocks 1 1 0 0 1 1 0 1 18 clocks 1 1 1 0 36 clocks figure 17-20 shows the communication reservation timing.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 438 figure 17-20. communication reservation timing 2 1 3456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iic0 set spd0 and intiic0 stt0 = 1 communi- cation reservation set std0 generate by master device with bus mastership remark iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after bit 1 (std0) of iic status register 0 (iics0) is set to 1, a communication reservation can be made by setting bit 1 (stt0) of iic control register 0 (iicc0) to 1 before a stop condition is detected. figure 17-21. timing for accepting communication reservations scl0 sda0 std0 spd0 standby mode figure 17-22 shows the communication reservation protocol.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 439 figure 17-22. communication reservation protocol di set1 stt0 define communication reservation wait msts0 = 0? (communication reservation) note yes no (generate start condition) cancel communication reservation mov iic0, # h ei sets stt0 flag (communication reservation) defines that communication reservation is in effect (defines and sets user flag to any part of ram) secures wait period set by software (see table 18-6 ). confirmation of communication reservation clear user flag iic0 write operation note the communication reservation operation executes a write to iic shift register 0 (iic0) when a stop condition interrupt request occurs. remark stt0: bit 1 of iic control register 0 (iicc0) msts0: bit 7 of iic status register 0 (iics0) iic0: iic shift register 0 (2) when communication reservation function is disabled (b it 0 (iicrsv) of iic flag register 0 (iicf0) = 1) when bit 1 (stt0) of iic control register 0 (iicc0) is se t to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. the following two statuses are included in the st atus where bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iicc0 was set to 1) to confirm whether the start conditi on was generated or request was rejected, check stcf (bit 7 of iicf0). the time shown in table 17-7 is required until stcf is se t to 1 after setting stt0 = 1. therefore, secure the time by software.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 440 table 17-7. wait periods cl01 cl00 wait period 0 0 6 clocks 0 1 6 clocks 1 0 12 clocks 1 1 3 clocks 17.5.15 other cautions (1) when stcen (bit 1 of iic flag register 0 (iicf0)) = 0 immediately after i 2 c operation is enabled (iice0 = 1), the bus comm unication status (iicb sy (bit 6 of iicf0) = 1) is recognized regardless of the actual bus status. when changing from a mode in which no stop condition has been detected to a master device communication mo de, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to per form master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. <1> set iic clock selection register 0 (iiccl0). <2> set bit 7 (iice0) of iic c ontrol register 0 (iicc0) to 1. <3> set bit 0 (spt0) of iicc0 to 1. (2) when stcen = 1 immediately after i 2 c operation is enabled (iice0 = 1), the bus released status (iicbsy = 0) is recognized regardless of the actual bus status. to generate the first start condition (stt0 (bit 1 of iic control register 0 (iicc0)) = 1), it is necessary to confirm that the bus has been releas ed, so as to not disturb other communications. (3) if other i 2 c communications are already in progress if i 2 c operation is enabled and the device participates in communication already in progress when the sda0 pin is low and the scl0 pin is high, the macro of i 2 c recognizes that the sda0 pin has gone low (detects a start condition). if the value on the bus at this time ca n be recognized as an extension code, ack is returned, but this interferes with other i 2 c communications. to avoid this, start i 2 c in the following sequence. <1> clear bit 4 (spie0) of iicc0 to 0 to disable gener ation of an interrupt request signal (intiic0) when the stop condition is detected. <2> set bit 7 (iice0) of iicc0 to 1 to enable the operation of i 2 c. <3> wait for detection of the start condition. <4> set bit 6 (lrel0) of iicc0 to 1 before ack is returned (4 to 80 clocks after setting iice0 to 1), to forcibly disable detection. (4) determine the transfer clock frequency by using sm c0, cl01, cl00 (bits 3, 1, and 0 of iicl0), and clx0 (bit 0 of iicx0) before enabling the operation (iice0 = 1). to change the transfer clock frequency, clear iice0 to 0 once.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 441 (5) setting stt0 and spt0 (bits 1 and 0 of iicc0) again afte r they are set and before they are cleared to 0 is prohibited. (6) when transmission is reserved, set spie0 (bit 4 of iicl0) to 1 so that an interrupt request is generated when the stop condit ion is detected. transfer is started wh en communication data is written to iic0 after the interrupt request is generated. unless th e interrupt is generated when the stop condition is detected, the device stops in the wait state beca use the interrupt request is not generated when communication is started. however, it is not necessary to set spie0 to 1 when msts0 (bit 7 of iics0) is detected by software.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 442 17.5.16 communication operations (1) master operation (single-master system) figure 17-23. master operation flowchart (single-master system) iicx0 0xh iiccl0 xxh iicf0 0xh setting stcen, iicrsv = 0 iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 setting port initializing i 2 c bus note spt0 = 1 sva0 xxh writing iic0 writing iic0 spt0 = 1 wrel0 = 1 start end reading iic0 acke0 = 0 wtim0 = wrel0 = 1 no no yes no no no yes yes yes yes stcen = 1? acke0 = 1 wtim0 = 0 intiic0 interrupt occurs? end of transfer? end of transfer? restart? trc0 = 1? ackd0 = 1? ackd0 = 1? sets each pin in the i 2 c mode (see 17.3 (7) port mode register 6 (pm6) ). selects a transfer clock. sets a local address. sets a start condition. prepares for starting communication (generates a start condition). starts communication (specifies an address and transfer direction). waits for detection of acknowledge. waits for data transmission. starts transmission. communication processing initial setting starts reception. waits for data reception. no yes intiic0 interrupt occurs? waits for detection of acknowledge. prepares for starting communication (generates a stop condition). waits for detection of the stop condition. no yes yes no intiic0 interrupt occurs? yes no intiic0 interrupt occurs? yes no yes no yes no intiic0 interrupt occurs? stt0 = 1 note release (scl0 and sda0 pins = high level) the i 2 c bus in conformance with t he specifications of the product that is communicating. if eeprom is outputting a low level to the sda0 pin, for example, set the scl0 pin in the output port mode, and output a clock pulse from the output port until the sda0 pin is constantly at high level. remark conform to the specifications of the product that is communicating, with respect to the transmission and reception formats.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 443 (2) master operation (multi-master system) figure 17-24. master operation flowchart (multi-master system) (1/3) iicx0 0xh iiccl0 xxh iicf0 0xh setting stcen and iicrsv iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 setting port spt0 = 1 sva0 xxh spie0 = 1 start slave operation slave operation releases the bus for a specific period. bus status is being checked. yes checking bus status note master operation starts? enables reserving communication. disables reserving communication. spd0 = 1? stcen = 1? iicrsv = 0? a sets each pin in the i 2 c mode (see 17.3 (7) port mode register 6 (pm6) ). selects a transfer clock. sets a local address. sets a start condition. (communication start request) (no communication start request) ? waiting to be specified as a slave by other master ? waiting for a communication start request (depends on user program) prepares for starting communication (generates a stop condition). waits for detection of the stop condition. no yes yes no intiic0 interrupt occurs? intiic0 interrupt occurs? yes no yes no spd0 = 1? yes no slave operation no intiic0 interrupt occurs? yes no 1 b spie0 = 0 yes no waits for a communication request. waits for a communication initial setting note confirm that the bus is released (cld0 bit = 1, dad0 bi t = 1) for a specific period (for example, for a period of one frame). if the sda0 pin is constantly at low level, decide whether to release the i 2 c bus (scl0 and sda0 pins = high level) in conformance with the s pecifications of the produc t that is communicating.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 444 figure 17-24. master operation flowchart (multi-master system) (2/3) stt0 = 1 wait slave operation yes msts0 = 1? exc0 = 1 or coi0 =1? prepares for starting communication (generates a start condition). secure wait time by software (see table 17-6 ). waits for bus release (communication being reserved). wait state after stop condition was detected and start condition was generated by the communication reservation function. no intiic0 interrupt occurs? yes yes no no a c stt0 = 1 wait slave operation yes iicbsy = 0? exc0 = 1 or coi0 =1? prepares for starting communication (generates a start condition). disables reserving communication. enables reserving communication. secure wait time by software (see table 18-7 ). waits for bus release detects a stop condition. no no intiic0 interrupt occurs? yes yes no yes stcf = 0? no b d c d communication processing communication processing
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 445 figure 17-24. master operation flowchart (multi-master system) (3/3) writing iic0 wtim0 = 1 wrel0 = 1 reading iic0 acke0 = 1 wtim0 = 0 wtim0 = wrel0 = 1 acke0 = 0 writing iic0 yes trc0 = 1? restart? msts0 = 1? starts communication (specifies an address and transfer direction). starts transmission. no yes waits for data reception. starts reception. yes no intiic0 i nterrupt occurs? yes no transfer end? waits for detection of ack. yes no intiic0 i nterrupt occurs? waits for data transmission. does not participate in communication. yes no intiic0 i nterrupt occurs? no yes ackd0 = 1? no yes no c 2 yes msts0 = 1? no yes transfer end? no yes ackd0 = 1? no 2 yes msts0 = 1? no 2 waits for detection of ack. yes no intiic0 i nterrupt occurs? yes msts0 = 1? no c 2 yes exc0 = 1 or coi0 = 1? no 1 2 spt0 = 1 stt0 = 1 slave operation end communication processing communication processing remarks 1. conform to the specifications of the product that is communicatin g, with respect to the transmission and reception formats. 2. to use the device as a master in a multi-master system, read the msts0 bit each time interrupt intiic0 has occurred to check the arbitration result. 3. to use the device as a slave in a multi-master system, check the status by using the iics0 and iicf0 registers each time interrupt intiic0 has occurr ed, and determine the processing to be performed next.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 446 (3) slave operation the processing procedure of the slave operation is as follows. basically, the slave operation is event-driven. therefor e, processing by the intiic0 interrupt (processing that must substantially change the operation status such as de tection of a stop condition during communication) is necessary. in the following explanation, it is assumed that the extension code is not supported for data communication. it is also assumed that the intiic0 interrupt servicing only performs status transition pr ocessing, and that actual data communication is performed by the main processing. iic0 interrupt servicing main processing intiic0 flag setting data setting therefore, data communication processing is perfo rmed by preparing the following three flags and passing them to the main processing instead of intiic0. <1> communication mode flag this flag indicates the following two communication statuses. ? clear mode: status in which data communication is not performed ? communication mode: status in which data comm unication is performed (from valid address detection to stop condition detection, no detec tion of ack from master, address mismatch) <2> ready flag this flag indicates that data communication is enabled. its function is the same as the intiic0 interrupt for ordinary data communication. this flag is set by interrupt servicing and cleared by the main processing. clear this flag by interrupt servicing when communication is started. however, the ready flag is not set by interrupt servicing when the first data is transmitted. therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> communication direction flag this flag indicates the direction of communic ation. its value is the same as trc0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 447 the main processing of the slave operation is explained next. start serial interface iic0 and wait until communication is enabled. when communication is enabled, execute communication by using the communication mode flag an d ready flag (processing of the stop condition and start condition is performed by an interrupt. here, check the status by using the flags). the transmission operation is repeated until the master no longer returns ack. if ack is not returned from the master, communication is completed. for reception, the necessary amount of data is received. when communication is completed, ack is not returned as the next data. after tha t, the master generates a stop condition or restart condition. exit from the communication status occurs in this way. figure 17-25. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no start communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 1? reading iic0 clearing ready flag clearing ready flag communication direction flag = 1? wrel0 = 1 ackd0 = 1? clearing communication mode flag wrel0 = 1 writing iic0 iicc0 xxh acke0 = wtim0 = 1 spie0 = 0, iice0 = 1 sva0 xxh sets a local address. iicx0 0xh iiccl0 xxh selects a transfer clock. iicf0 0xh setting iicrsv sets a start condition. starts transmission. starts reception. no yes no communication mode flag = 1? yes no ready flag = 1? remark conform to the specifications of the product that is in communication, regarding the transmission and reception formats.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 448 an example of the processing procedur e of the slave with the intiic0 inte rrupt is explained below (processing is performed assuming that no extension code is used). the intiic0 interrupt c hecks the status, and the following operations are performed. <1> communication is stopped if the stop condition is issued. <2> if the start condition is issued, the address is c hecked and communication is completed if the address does not match. if the address matches, the communi cation mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> for data transmit/receive, only the ready flag is set. processing returns from the interrupt with the i 2 c bus remaining in the wait state. remark <1> to <3> above correspond to <1> to <3> in figure 17-26 slave operation flowchart (2) . figure 17-26. slave operation flowchart (2) yes yes yes no no no intiic0 generated set ready flag interrupt servicing completed spd0 = 1? std0 = 1? coi0 = 1? communication direction flag trc0 set communication mode flag clear ready flag clear c ommunication direction flag, ready flag, and communication mode flag <1> <2> <3>
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 449 17.5.17 timing of i 2 c interrupt request (intiic0) occurrence the timing of transmitting or receiving data and generation of interrupt request signal in tiic0, and the value of the iics0 register when the intiic0 signal is generated are shown below. remark st: start condition ad6 to ad0: address r/w: transfer direction specification ack: acknowledge d7 to d0: data sp: stop condition
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 450 (1) master device operation (a) start ~ address ~ data ~ data ~ stop (transmission/reception) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b 3: iics0 = 1000000b (sets wtim0 to 1) note 4: iics0 = 100000b (sets spt0 to 1) note 5: iics0 = 00000001b note to generate a stop condition, set wtim0 to 1 and chan ge the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b 3: iics0 = 100000b (sets spt0 to 1) 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 451 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt0 = 1 spt0 = 1 3 4 7 2 1 5 6 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) note 1 3: iics0 = 100000b (clears wtim0 to 0 note 2 , sets stt0 to 1) 4: iics0 = 1000110b 5: iics0 = 1000000b (sets wtim0 to 1) note 3 6: iics0 = 100000b (sets spt0 to 1) 7: iics0 = 00000001b notes 1. to generate a start condition, set wtim0 to 1 and change the timing for generating the intiic0 interrupt request signal. 2. clear wtim0 to 0 to restore the original setting. 3. to generate a stop condition, set wtim0 to 1 and change the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt0 = 1 spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 100000b (sets stt0 to 1) 3: iics0 = 1000110b 4: iics0 = 100000b (sets spt0 to 1) 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 452 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 5 2 1 1: iics0 = 1010110b 2: iics0 = 1010000b 3: iics0 = 1010000b (sets wtim0 to 1) note 4: iics0 = 101000b (sets spt0 to 1) 5: iics0 = 00000001b note to generate a stop condition, set wtim0 to 1 and chan ge the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 2 1 1: iics0 = 1010110b 2: iics0 = 1010100b 3: iics0 = 101000b (sets spt0 to 1) 4: iics0 = 00001001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 453 (2) slave device operation (slave address data reception) (a) start ~ address ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0001000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001100b 3: iics0 = 000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 454 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0001110b 4: iics0 = 0001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 0001110b 4: iics0 = 000100b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 455 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0010010b 4: iics0 = 0010000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 5 6 2 1 4 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 0010010b 4: iics0 = 0010110b 5: iics0 = 001000b 6: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 456 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 457 (3) slave device operation (w hen receiving extension code) the device is always participating in communication when it receives an extension code. (a) start ~ code ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0010000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 0010100b 4: iics0 = 001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 458 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0001110b 4: iics0 = 0001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, matches sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 6 2 1 5 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 001000b 4: iics0 = 0001110b 5: iics0 = 000100b 6: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 459 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0010010b 4: iics0 = 0010000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 7 2 1 5 6 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 001000b 4: iics0 = 0010010b 5: iics0 = 0010110b 6: iics0 = 001000b 7: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 460 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 00100010b 2: iics0 = 00100000b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 00100010b 2: iics0 = 00100110b 3: iics0 = 0010000b 4: iics0 = 00000110b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 461 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 1 1: iics0 = 00000001b remark : generated only when spie0 = 1 (5) arbitration loss operation (opera tion as slave after arbitration loss) when the device is used as a master in a multi-master system, read the ms ts0 bit each time interrupt request signal intiic0 has occurred to check the arbitration result. (a) when arbitration loss occurs durin g transmission of slave address data (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0101110b 2: iics0 = 0001000b 3: iics0 = 0001000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 462 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0101110b 2: iics0 = 0001100b 3: iics0 = 000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (b) when arbitration loss occurs dur ing transmission of extension code (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0110010b 2: iics0 = 0010000b 3: iics0 = 0010000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 463 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics0 = 0110010b 2: iics0 = 0010110b 3: iics0 = 0010100b 4: iics0 = 001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (6) operation when arbitration loss occurs (no communication after arbitration loss) when the device is used as a master in a multi-master system, read the ms ts0 bit each time interrupt request signal intiic0 has occurred to check the arbitration result. (a) when arbitration loss occu rs during transmission of slave address data (when wtim0 = 1) st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics0 = 01000110b 2: iics0 = 00000001b remark : always generated : generated only when spie0 = 1
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 464 (b) when arbitration loss occurs dur ing transmission of extension code st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics0 = 0110010b sets lrel0 = 1 by software 2: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (c) when arbitration loss occu rs during transmission of data (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics0 = 10001110b 2: iics0 = 01000000b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 465 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics0 = 10001110b 2: iics0 = 01000100b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (d) when loss occurs due to rest art condition during data transfer (i) not extension code (example: unmatches with sva0) st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics0 = 1000110b 2: iics0 = 01000110b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 466 (ii) extension code st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics0 = 1000110b 2: iics0 = 01100010b sets lrel0 = 1 by software 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0 (e) when loss occurs due to st op condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp 2 1 1: iics0 = 10000110b 2: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 467 (f) when arbitration loss occurs due to low-level da ta when attempting to generate a restart condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 1000100b (clears wtim0 to 0) 4: iics0 = 01000000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b (sets stt0 to 1) 3: iics0 = 01000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 468 (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 ack sp stt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 100000b (sets stt0 to 1) 4: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp stt0 = 1 2 3 1 1: iics0 = 1000110b 2: iics0 = 100000b (sets stt0 to 1) 3: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 469 (h) when arbitration loss occurs due to low-level data when attemp ting to generate a stop condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 1000100b (clears wtim0 to 0) 4: iics0 = 01000100b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b (sets spt0 to 1) 3: iics0 = 01000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 470 17.6 timing charts when using the i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the mast er device transmits the trc0 bit (bit 3 of iic status register 0 (iics0)), which specifies the data transfer di rection, and then starts serial communication with the slave device. figures 17-27 and 17-28 show timing charts of the data communication. iic shift register 0 (iic0)?s shift operation is synchronized with the falling edge of the serial clock (scl0). the transmit data is transferred to the so0 latch a nd is output (msb first) via the sda0 pin. data input via the sda0 pin is captured into iic0 at the rising edge of scl0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 471 figure 17-27. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (1/3) (1) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic0 address iic0 data iic0 ffh transmit start condition receive (when exc0 = 1) note note note to cancel slave wait, write ?ffh? to iic0 or set wrel0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 472 figure 17-27. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (2/3) (2) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data iic0 ffh iic0 ffh iic0 data transmit receive note note ack ack note note note to cancel slave wait, write ?ffh? to iic0 or set wrel0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 473 figure 17-27. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (3/3) (3) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie0 = 1) receive (when spie0 = 1) ack note to cancel slave wait, write ?ffh? to iic0 or set wrel0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 474 figure 17-28. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (1/3) (1) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note note iic0 data start condition ack note to cancel master wait, write ?ffh? to iic0 or set wrel0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 475 figure 17-28. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (2/3) (2) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l l h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note note to cancel master wait, write ?ffh? to iic0 or set wrel0.
chapter 17 serial interface iic0 preliminary user?s manual u17260ej3v1ud 476 figure 17-28. example of slave to master communication (when 8-clock and 9-clock wait is selected for m aster, 9-clock wait is selected for slave) (3/3) (3) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie0 = 1) nack (when spie0 = 1) note to cancel master wait, write ?ffh? to iic0 or set wrel0.
preliminary user?s manual u17260ej3v1ud 477 chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) only for the pd78f0534, 78f0535, 78f0536, 78f 0537, and 78f0537d, the multiplier/divider is provided. 18.1 functions of multiplier/divider the multiplier/divider has the following functions. ? 16 bits 16 bits = 32 bits (multiplication) ? 32 bits 16 bits = 32 bits, 16-bit remainder (division) 18.2 configuration of multiplier/divider the multiplier/divider incl udes the following hardware. table 18-1. configuration of multiplier/divider item configuration registers remainder data register 0 (sdr0) multiplication/division data r egisters a0 (mda0h, mda0l) multiplication/division dat a registers b0 (mdb0) control register multiplier/divider control register 0 (dmuc0) figure 18-1 shows the block diagram of the multiplier/divider.
chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 478 figure 18-1. block diagra m of multiplier/divider internal bus cpu clock start clear 17-bit adder controller multiplication/division data register b0 (mdb0 (mdb0h + mdb0l) remainder data register 0 (sdr0 (sdr0h + sdr0l) 6-bit counter dmusel0 multiplier/divider control register 0 (dmuc0) controller multiplication/division data register a0 ( mda0h (mda0hh + mda0hl) + mda0l (mda0lh + mda0ll) ) controller dmue mda000 intdmu
chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 479 (1) remainder data register 0 (sdr0) sdr0 is a 16-bit register that stores a remainder. th is register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. sdr0 can be read by an 8-bit or 16-bit memory manipulation instruction. reset signal generation sets sdr0 to 0000h. figure 18-2. format of remainder data register 0 (sdr0) address: ff60h, ff61h after reset: 0000h r symbol ff61h (sdr0h) ff60h (sdr0l) sdr0 sdr 015 sdr 014 sdr 013 sdr 012 sdr 011 sdr 010 sdr 009 sdr 008 sdr 007 sdr 006 sdr 005 sdr 004 sdr 003 sdr 002 sdr 001 sdr 000 cautions 1. the value read from sdr0 duri ng operation processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1) is not guaranteed. 2. sdr0 is reset when the operation is started (when dmue is set to 1). (2) multiplication/division data register a0 (mda0h, mda0l) mda0 is a 32-bit register that sets a 16-bit multiplier a in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the oper ation (higher 16 bits: mda0h, lower 16 bits: mda0l). figure 18-3. format of mult iplication/division data regi ster a0 (mda0h, mda0l) address: ff62h, ff63h, ff64h, ff65h after reset: 0000h, 0000h r/w symbol ff65h (mda0hh) ff64h (mda0hl) mda0h mda 031 mda 030 mda 029 mda 028 mda 027 mda 026 mda 025 mda 024 mda 023 mda 022 mda 021 mda 020 mda 019 mda 018 mda 017 mda 016 symbol ff63h (mda0lh) ff62h (mda0ll) mda0l mda 015 mda 014 mda 013 mda 012 mda 011 mda 010 mda 009 mda 008 mda 007 mda 006 mda 005 mda 004 mda 003 mda 002 mda 001 mda 000 cautions 1. mda0h is cleared to 0 when an operation is starte d in the multiplication mode (when multiplier/divider control regist er 0 (dmuc0) is set to 81h). 2. do not change the value of mda0 duri ng operation processing (whi le bit 7 (dmue) of multiplier/divider control regi ster 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. 3. the value read from mda0 during operation processi ng (while dmue is 1) is not guaranteed.
chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 480 the functions of mda0 when an operation is executed are shown in the table below. table 18-2. functions of mda0 during operation execution dmusel0 operation mode setting operation result 0 division mode di vidend division result (quotient) 1 multiplication mode higher 16 bits: 0, lower 16 bits: multiplier a multiplication result (product) the register configuration differs between when multiplication is executed and when division is executed, as follows. ? register configuration during multiplication mda0 (bits 15 to 0) mdb0 (bits 15 to 0) = mda0 (bits 31 to 0) ? register configuration during division mda0 (bits 31 to 0) mdb0 (bits 15 to 0) = mda0 (bit s 31 to 0) ? sdr0 (bits 15 to 0) mda0 fetches the calculation result as soon as the cloc k is input, when bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is set to 1. mda0h and mda0l can be set by an 8-bit or 16-bit memory manipulation instruction. reset signal generation clears mda0h and mda0l to 0000h. (3) multiplication/division data register b0 (mdb0) mdb0 is a register that stores a 16 -bit multiplier b in the multiplicat ion mode and a 16-bit divisor in the division mode. mdb0 can be set by an 8-bit or 16-bit memory manipulation instruction. reset signal generation sets mdb0 to 0000h. figure 18-4. format of multiplicatio n/division data register b0 (mdb0) address: ff66h, ff67h after reset: 0000h r/w symbol ff67h (mdb0h) ff66h (mdb0l) mdb0 mdb 015 mdb 014 mdb 013 mdb 012 mdb 011 mdb 010 mdb 009 mdb 008 mdb 007 mdb 006 mdb 005 mdb 004 mdb 003 mdb 002 mdb 001 mdb 000 cautions 1. do not change the value of mdb0 during operation processing (while bit 7 (dmue) of multiplier/divider control regi ster 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. 2. do not clear mdb0 to 00 00h in the division mode. if set, undefined operation results are stored in mda0 and sdr0.
chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 481 18.3 register controlling multiplier/divider the multiplier/divider is controlled by mult iplier/divider control register 0 (dmuc0). (1) multiplier/divider c ontrol register 0 (dmuc0) dmuc0 is an 8-bit register that controls the operation of the multiplier/divider. dmuc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets dmuc0 to 00h. figure 18-5. format of multiplier/divider control register 0 (dmuc0) dmue dmuc0 0 0 0 0 0 0 dmusel0 stops operation starts operation dmue note 0 1 operation start/stop division mode multiplication mode dmusel0 0 1 operation mode (multiplication/division) selection address: ff68h after reset: 00h r/w symbol 4 3 2 1 0 6 <7> 5 note when dmue is set to 1, the operati on is started. dmue is automatically cleared to 0 after the operation is complete. cautions 1. if dmue is cleared to 0 during ope ration processing (when dmue is 1), the operation result is not guaranteed. if the operation is comp leted while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. do not change the value of dmusel0 during operation processing (w hile dmue is 1). if it is changed, undefined operation r esults are stored in multiplicat ion/division data register a0 (mda0) and remainder data register 0 (sdr0). 3. if dmue is cleared to 0 during opera tion processing (while dmue is 1), the operation processing is stopped. to execute the operati on again, set multiplication/division data register a0 (mda0), multiplication/division data register b0 (mdb0), and multiplier/divider control register 0 (dmuc0), and star t the operation (by setting dmue to 1).
chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 482 18.4 operations of multiplier/divider 18.4.1 multiplication operation ? initial setting 1. set operation data to multiplicati on/division data register a0l (mda0l) a nd multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divi der control register 0 (dmuc0) to 1. operation will start. ? during operation 3. the operation will be completed when 16 internal clocks have been issued after the start of the operation (intermediate data is stored in t he mda0l and mda0h registers during operation, and t herefore the read values of these registers are not guaranteed). ? end of operation 4. the operation result data is stor ed in the mda0l and mda0h registers. 5. dmue is cleared to 0 (end of operation). 6. after the operation, an interrup t request signal (intdmu) is generated. ? next operation 7. to execute multiplication next, start from the initial setting in 18.4.1 multiplication operation . 8. to execute division next, start from the initial setting in 18.4.2 division operation .
chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 483 figure 18-6. timing chart of multiplication operation (00dah 0093h) operation clock mda0 sdr0 mdb0 1 2 345 6 78 9a b cd e f 10 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 006d 0000 00da xxxx 00da xxxx xxxx xxxx 0049 8036 0024 c01b 005b e00d 0077 7006 003b b803 0067 5c01 007d 2e00 003e 9700 001f 4b80 000f a5c0 0007 d2e0 0003 e970 0001 f4b8 0000 fa5c 0000 7d2e 0093 xxxx internal clock dmue dmusel0 counter intdmu
chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 484 18.4.2 division operation ? initial setting 1. set operation data to multiplicati on/division data register a0 (mda0l and mda0h) and multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divider control register 0 (dmuc0) to 0 and 1, respectively. operation will start. ? during operation 3. the operation will be completed when 32 internal clocks have been issued after the start of the operation (intermediate data is stored in the mda0l and mda0 h registers and remainder data register 0 (sdr0) during operation, and theref ore the read values of these registers are not guaranteed). ? end of operation 4. the result data is stored in th e mda0l, mda0h, and sdr0 registers. 5. dmue is cleared to 0 (end of operation). 6. after the operation, an interrup t request signal (intdmu) is generated. ? next operation 7. to execute multiplication next, start from the initial setting in 18.4.1 multiplication operation . 8. to execute division next, start from the initial setting in 18.4.2 division operation .
chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) preliminary user?s manual u17260ej3v1ud 485 figure 18-7. timing chart of division operation (dcba2586h 0018h) operation clock mda0 sdr0 mdb0 12345678 19 1a 1b 1c 1d 1e 1f 20 0 0 0000 0001 0003 0006 000d 0003 0007 000e 0004 000b 0016 0014 0010 0008 0011 000b 0016 b974 4b0c dcba 2586 xxxx xxxx xxxx 72e8 9618 e5d1 2c30 cba2 5860 9744 b0c1 2e89 6182 5d12 c304 ba25 8609 0c12 64d8 1824 c9b0 3049 9361 6093 26c3 c126 4d87 824c 9b0e 0499 361d 0932 6c3a 0018 xxxx internal clock dmue dmusel0 counter intdmu ?0?
preliminary user?s manual u17260ej3v1ud 486 chapter 19 interrupt functions 19.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrup ts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l, pr1h). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored in terrupt servicing. for the priority order, see table 19-1 . a standby release signal is generated a nd stop and halt modes are released. external interrupt requests and internal interrupt requests are provided as maskable interrupts. ? pd78f0531, 78f0532, 78f0533 external: 9, internal: 16 ? pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d external: 9, internal: 19 (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 19.2 interrupt sources and configuration the pd78f0531, 78f0532, and 78f0533 have a to tal of 26 interrupt sources, and the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d have a total of 29 interrupt sources, including maskable interrupts and software interrupts. in addition, they also have up to four reset sources (see table 19-1 ).
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 487 table 19-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection note 3 internal 0004h (a) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 pin input edge detection external 0010h (b) 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 intcsi10/ intst0 end of csi10 communication/end of uart0 transmission 0018h 11 inttmh1 match between tmh1 and cmp01 (when compare register is specified) 001ah 12 inttmh0 match between tmh0 and cmp00 (when compare register is specified) 001ch 13 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 14 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 0020h 15 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 0022h 16 intad end of a/d conversion 0024h 17 intsr0 end of uart0 reception or reception error generation 0026h 18 intwti watch timer referenc e time interval signal 0028h 19 inttm51 match between tm51 and cr51 (when compare register is specified) internal 002ah (a) 20 intkr key interrupt detection external 002ch (c) 21 intwt watch timer overflow internal 002eh (a) 22 intp6 0030h maskable 23 intp7 pin input edge detection external 0032h (b) notes 1. the default priority determines t he sequence of processing vectored in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the hi ghest priority and 27 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 19-1. 3. when bit 1 (lvimd) of the low-voltage det ection register (lvim) is cleared to 0.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 488 table 19-1. interrupt source list (2/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 24 intiic0/ intdmu note 3 end of iic0 communication/end of multiply/divide operation 0034h 25 intcsi11 note 3 end of csi11 communication 0036h 26 inttm001 note 3 match between tm01 and cr001 (when compare register is specified), ti011 pin valid edge detection (when capture register is specified) 0038h maskable 27 inttm011 note 3 match between tm01 and cr011 (when compare register is specified), ti001 pin valid edge detection (when capture register is specified) internal 003ah (a) software ? brk brk instruction execution ? 003eh (d) reset reset input poc power-on clear lvi low-voltage detection note 4 reset ? wdt wdt overflow ? 0000h ? notes 1. the default priority is the priority applicable w hen two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 27 is the lowest. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 19-1. 3. the interrupt sources intdmu, intcsi11, in ttm001, and inttm011 are available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d. 4. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 489 figure 19-1. basic configurati on of interrupt function (1/2) (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable inte rrupt (intp0 to intp7) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 490 figure 19-1. basic configurati on of interrupt function (2/2) (c) external maskable interrupt (intkr) if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal key interrupt detector 1 when krmn = 1 (n = 0 to 7) (d) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag krm: key return mode register
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 491 19.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag regist er (if0l, if0h, if1l, if1h) ? interrupt mask flag register (mk0l, mk0h, mk1l, mk1h) ? priority specification flag register (pr0l, pr0h, pr1l, pr1h) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 19-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 492 table 19-2. flags corresponding to interrupt request sources interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intsre6 sreif6 sremk6 srepr6 intsr6 srif6 if0h srmk6 mk0h srpr6 pr0h intst6 stif6 stmk6 stpr6 intcsi10 csiif10 csimk10 csipr10 intst0 stif0 dualif0 note 1 stmk0 dualmk0 note 2 stpr0 dualpr0 note 2 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 intad adif if1l admk mk1l adpr pr1l intsr0 srif0 srmk0 srpr0 intwti wtiif wtimk wtipr inttm51 tmif51 tmmk51 tmpr51 intkr krif krmk krpr intwt wtif wtmk wtpr intp6 pif6 pmk6 ppr6 intp7 pif7 pmk7 ppr7 intiic0 iicif0 iicmk0 iicpr0 intdmu note 3 dmuif note 3 if1h dmumk note 3 mk1h dmupr note 3 pr1h intcsi11 note 3 csiif11 note 3 csimk11 note 3 csipr11 note 3 inttm001 note 3 tmif001 note 3 tmmk001 note 3 tmpr001 note 3 inttm011 note 3 tmif011 note 3 tmmk011 note 3 tmpr011 note 3 notes 1. if either interrupt source intcsi10 or ints t0 is generated, these flags are set (1). 2. both interrupt sources intcsi10 and intst0 are supported. 3. pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 493 (1) interrupt request flag regist ers (if0l, if0h, if1l, if1h) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknow ledgment of an interrupt request or upon reset signal generation. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, and if1h are set by a 1-bit or 8-bit memory manipulation instruct ion. when if0l and if0h, and if1l and if1h are combined to form 16-bit registers if0 and if1, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 19-2. format of interrupt request fl ag registers (if0l, if0h, if1l, if1h) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 csiif10 stif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l pif7 pif6 wtif krif tmif51 wtiif srif0 adif address: ffe3h after reset: 00h r/w symbol 7 6 5 4 <3> <2> <1> <0> if1h 0 0 0 0 tmif011 note tmif001 note csiif11 note iicif0 dmuif note xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status note pd78f0534, 78f0535, 78f 0536, 78f0537, and 78f0537d only. cautions 1. be sure to clear bi ts 1 to 7 of if1h to 0 for the pd78f0531, 78f0532, and 78f0533. be sure to clear bits 4 to 7 of if1h to 0 for the pd78f0534, 78f0535, 78f 0536, 78f0537, and 78f0537d. 2. when operating a timer, se rial interface, or a/d converter after standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 494 cautions 3. when manipulating a flag of the in terrupt request flag regi ster, use a 1-bit memory manipulation instruction (clr1). when descr ibing in c language, use a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the co mpiled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language usi ng an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it becom es the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?mov a, if0l? and ?mov if 0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care must be exercised when us ing an 8-bit memory manipulation instruction in c language.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 495 (2) interrupt mask flag regist ers (mk0l, mk0h, mk1l, mk1h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, and mk1h are set by a 1-bit or 8- bit memory manipulation instruction. when mk0l and mk0h, and mk1l and mk1h are combined to form 16-bit registers mk0 and mk1, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 19-3. format of interrupt mask fl ag registers (mk0l, mk0h, mk1l, mk1h) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 csimk0 stmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l pmk7 pmk6 wtmk krmk tmmk51 wtimk srmk0 admk address: ffe7h after reset: ffh r/w symbol 7 6 5 4 <3> <2> <1> <0> mk1h 1 1 1 1 tmmk011 note tmmk001 note csimk11 note iicmk0 dmumk note xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled note pd78f0534, 78f0535, 78f 0536, 78f0537, and 78f0537d only. caution be sure to set bits 1 to 7 of mk1h to 1 for the pd78f0531, 78f0532, and 78f 0533. be sure to set bits 4 to 7 of mk1h to 1 for the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 496 (3) priority specification flag re gisters (pr0l, pr0h, pr1l, pr1h) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, pr1l, and pr1h are set by a 1-bit or 8-bi t memory manipulation instruction. if pr0l and pr0h, and pr1l and pr1h are combined to form 16-bit registers pr0 and pr1, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 19-4. format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpr0 csipr10 stpr0 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr1l ppr7 ppr6 wtpr krpr tmpr51 wtipr srpr0 adpr address: ffebh after reset: ffh r/w symbol 7 6 5 4 <3> <2> <1> <0> pr1h 1 1 1 1 tmpr011 note tmpr001 note csipr11 note iicpr0 dmupr note xxprx priority level selection 0 high priority level 1 low priority level note pd78f0534, 78f0535, 78f 0536, 78f0537, and 78f0537d only. caution be sure to set bits 1 to 7 of pr1h to 1 for the pd78f0531, 78f0532, and 78f 0533. be sure to set bits 4 to 7 of pr1h to 1 for the pd78f0534, 78f0535, 78f053 6, 78f0537, and 78f0537d.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 497 (4) external interrupt rising edge en able register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp7. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to 00h. figure 19-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp egp7 egp6 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 7) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 19-3 shows the ports corresponding to egpn and egnn. table 19-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120 intp0 egp1 egn1 p30 intp1 egp2 egn2 p31 intp2 egp3 egn3 p32 intp3 egp4 egn4 p33 intp4 egp5 egn5 p16 intp5 egp6 egn6 p140 intp6 egp7 egn7 p141 intp7 caution select the port mode by clearing eg pn and egnn to 0 because an edge may be detected when the external interrupt func tion is switched to the port function. remark n = 0 to 7
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 498 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable interr upt enable/disable and the isp fl ag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with t he push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset signal generation sets psw to 02h. figure 19-6. format of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 2 0 <1> isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 499 19.4 interrupt servicing operations 19.4.1 maskable interrupt acknowledgement a maskable interrupt becomes acknowledgeable when the in terrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority in terrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until vectored interr upt servicing is performed are listed in table 19-4 below. for the interrupt request acknowledgement timing, see figures 19-8 and 19-9 . table 19-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a di vide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledge d first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 19-7 shows the interrupt request acknowledgement algorithm. if a maskable interrupt request is acknowledged, the content s are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the pr iority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. the vector table data deter mined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 500 figure 19-7. interrupt request ac knowledgement pr ocessing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgement of mask able interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledg ed, or low-priority interrupt servicing)
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 501 figure 19-8. interrupt request ac knowledgement timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 19-9. interrupt request ac knowledgement timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 19.4.2 software interrupt request acknowledgement a software interrupt acknowledge is acknowledged by brk instruction execution. so ftware interrupts cannot be disabled. if a software interrupt request is ackno wledged, the cont ents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and t he contents of the ve ctor table (003eh, 003fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt.
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 502 19.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the in terrupt request acknowledgem ent enabled state is selected (ie = 1). when an interrupt request is acknowledged, interrupt request acknow ledgement becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgement. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. inte rrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower prio rity are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 19-10 shows multiple interrupt servicing examples. table 19-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp = 0 { { maskable interrupt isp = 1 { { { software interrupt { { { remarks 1. : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgement is disabled. ie = 1: interrupt request acknowledgement is enabled. 4. pr is a flag contained in pr0l, pr0h, pr1l, and pr1h. pr = 0: higher priority level pr = 1: lower priority level
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 503 figure 19-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt re quest is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 504 figure 19-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgement disabled
chapter 19 interrupt functions preliminary user?s manual u17260ej3v1ud 505 19.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until t he end of execution of the next instruction. these instructions (interrupt request hol d instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ? ei ? di ? manipulation instructions for the if0l, if0h, if1l, if1h, mk0l, mk0h, mk1l, mk1h, pr0l, pr0h, pr1l, and pr1h registers. caution the brk instruction is not one of the above-listed interrupt re quest hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt re quest is generated during execution of the brk instruction, the interrupt re quest is not acknowledged. figure 19-11 shows the timing at which interrupt requests are held pending. figure 19-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request).
preliminary user?s manual u17260ej3v1ud 506 chapter 20 key interrupt function 20.1 functions of key interrupt a key interrupt (intkr) can be generated by setting t he key return mode register (krm) and inputting a falling edge to the key interrupt input pins (kr0 to kr7). table 20-1. assignment of k ey interrupt detection pins flag description krm0 controls kr0 signal in 1-bit units. krm1 controls kr1 signal in 1-bit units. krm2 controls kr2 signal in 1-bit units. krm3 controls kr3 signal in 1-bit units. krm4 controls kr4 signal in 1-bit units. krm5 controls kr5 signal in 1-bit units. krm6 controls kr6 signal in 1-bit units. krm7 controls kr7 signal in 1-bit units. 20.2 configuration of key interrupt the key interrupt includes the following hardware. table 20-2. configuration of key interrupt item configuration control register key return mode register (krm) figure 20-1. block diag ram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
chapter 20 key interrupt function preliminary user?s manual u17260ej3v1ud 507 20.3 register controlling key interrupt (1) key return mode register (krm) this register controls the krm0 to krm7 bits using the kr0 to kr7 signals, respectively. krm is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets krm to 00h. figure 20-2. format of key return mode register (krm) krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: ff6eh after reset: 00h r/w symbol 765432 0 cautions 1. if any of the krm0 to krm7 bits used is set to 1, set bits 0 to 7 (pu70 to pu77) of the corresponding pull-up resistor register 7 (pu7) to 1. 2. if krm is changed, the interrupt request flag may be set. therefore, disable interrupts and then change the krm register. clear the in terrupt request flag and enable interrupts. 3. the bits not used in the key inte rrupt mode can be used as normal ports.
preliminary user?s manual u17260ej3v1ud 508 chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function the standby function is designed to reduce the operating current of the system. the following two modes are available. (1) halt mode halt instruction execution se ts the halt mode. in the halt mode, the cpu operation clock is stopped. if the high-speed system clock oscillator, in ternal high-speed oscillator, internal low-speed oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock continues. in this mode, the operating current is not decreased as much as in the st op mode, but the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released when the x1 clock is selected, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. the stop mode can be used only when the cpu is operating on the main system clock. the subsystem clock oscillation cannot be stopped. the halt mode can be used when the cpu is operating on either the main syst em clock or the subsystem clock. 2. when shifting to the stop mode, be su re to stop the peripher al hardware operation operating with main system clock be fore executing stop instruction. 3. the following sequence is r ecommended for operating current reduction of the a/d converter when the standby function is used: first cl ear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion opera tion, and then execute the stop instruction. 21.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 6 clock generator .
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 509 (1) oscillation stabilization time c ounter status register (ostc) this is the register that indicates t he count status of the x1 clock oscillati on stabilization time counter. when x1 clock oscillation starts with the intern al high-speed oscillation clock or su bsystem clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 21-1. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status f x = 10 mhz f x = 20 mhz 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 0 0 2 14 /f x min. 1.64 ms min. 819.2 s min. 1 1 1 1 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 2 16 /f x min. 6.55 ms min. 3.27 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 510 (2) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elaps ed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 21-2. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 10 mhz f x = 20 mhz 0 0 1 2 11 /f x 204.8 s 102.4 s 0 1 0 2 13 /f x 819.2 s 409.6 s 0 1 1 2 14 /f x 1.64 ms 819.2 s 1 0 0 2 15 /f x 3.27 ms 1.64 ms 1 0 1 2 16 /f x 6.55 ms 3.27 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 4. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 511 21.2 standby function operation 21.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the high-spe ed system clock, internal high-spee d oscillation clock, or subsystem clock. the operating statuses in t he halt mode are shown below.
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 512 table 21-1. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on main system clock halt mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh operation continues (cannot be stopped) status before halt mode was set is retained f x status before halt mode was set is retained operation continues (cannot be stopped) status before halt mode was set is retained main system clock f exclk operates or stops by external cl ock input operation continues (cannot be stopped) f xt status before halt mode was set is retained subsystem clock f exclks operates or stops by external clock input f rl status before halt mode was set is retained cpu operation stopped flash memory operation stopped ram status before halt mode was set is retained port (latch) status before halt mode was set is retained 00 16-bit timer/event counter 01 note 50 8-bit timer/event counter 51 h0 8-bit timer h1 watch timer operable watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output buzzer output a/d converter uart0 uart6 csi10 csi11 note serial interface iic0 multiplier/divider note power-on-clear function low-voltage detection function external interrupt operable note pd78f0534, 78f0535, 78f0536, 78 f0537, and 78f0537d only. remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f exclks : external subsystem clock f rl : internal low-speed oscillation clock
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 513 table 21-1. operating statuses in halt mode (2/2) when halt instruction is executed while cpu is operating on subsystem clock halt mode setting item when cpu is operating on xt1 clock (f xt ) when cpu is operating on external subsystem clock (f exclks ) system clock clock supply to the cpu is stopped f rh f x status before halt mode was set is retained main system clock f exclk operates or stops by external clock input f xt operation continues (cannot be stopped) stat us before halt mode was set is retained subsystem clock f exclks operates or stops by external clock input operation continues (cannot be stopped) f rl status before halt mode was set is retained cpu operation stopped flash memory operation stopped ram status before halt mode was set is retained port (latch) status before halt mode was set is retained 00 note1 16-bit timer/event counter 01 note1. 2 50 note1 8-bit timer/event counter 51 note1 h0 8-bit timer h1 watch timer operable watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output operable buzzer output a/d converter operable. however, operation dis abled when peripheral hardware clock (f prs ) is stopped. uart0 uart6 csi10 note1 csi11 note1, 2 serial interface iic0 note1 multiplier/divider note2 power-on-clear function low-voltage detection function external interrupt operable notes 1. when the cpu is operating on the subsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of thes e functions on the external clock input from peripheral hardware pins. 2. pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only. remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f exclks : external subsystem clock f rl : internal low-speed oscillation clock
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 514 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgement is enabled, vectored interrupt servici ng is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 21-3. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation high-speed system clock, internal high-speed oscillation clock, or subsystem clock status of cpu standby release signal interrupt request remarks 1. the broken lines indicate the case when the in terrupt request which has released the standby mode is acknowledged. 2. the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 515 (b) release by reset signal generation when the reset signal is generated, halt mode is re leased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 21-4. halt mode release by reset (1) when high-speed system clock is used as cpu clock halt instruction reset signal high-speed system clock (x1 oscillation) halt mode reset period oscillates oscillation stopped oscillates status of cpu normal operation (high-speed system clock) oscillation stabilization time (2 11 /f x to 2 16 /f x ) normal operation (internal high-speed oscillation clock) oscillation stopped starting x1 oscillation is specified by software. reset processing (20 s (typ.)) (2) when internal high-speed osc illation clock is used as cpu clock halt instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) halt mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu wait for oscillation accuracy stabilization reset processing (20 s (typ.)) (3) when subsystem clo ck is used as cpu clock halt instruction reset signal subsystem clock (xt1 oscillation) normal operation (subsystem clock) halt mode reset period normal operation mode (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stopped starting xt1 oscillation is specified by software. reset processing (20 s (typ.)) remark f x : x1 clock oscillation frequency
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 516 table 21-2. operation in response to interrupt request in halt mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 halt mode held reset ? ? reset processing : don?t care 21.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction, and it can be se t only when the cpu clock before the setting was the main system clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. the operating statuses in t he stop mode are shown below.
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 517 table 21-3. operating statuses in stop mode when stop instruction is executed while cpu is operating on main system clock stop mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh f x stopped main system clock f exclk input invalid f xt status before stop mode was set is retained subsystem clock f exclks operates or stops by external clock input f rl status before stop mode was set is retained cpu operation stopped flash memory operation stopped ram status before stop mode was set is retained port (latch) status before stop mode was set is retained 00 16-bit timer/event counter 01 note operation stopped 50 operable only when ti50 is selected as the count clock 8-bit timer/event counter 51 operable only when ti51 is selected as the count clock h0 operable only when tm50 output is selected as the count clock during 8- bit timer/event counter 50 operation 8-bit timer h1 operable only when f rl , f rl /2 7 , f rl /2 9 is selected as the count clock watch timer operable only when subsystem clock is selected as the count clock watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output operable only w hen subsystem clock is selected as the count clock buzzer output a/d converter operation stopped uart0 uart6 operable only when tm50 output is selected as the serial clock during 8-bi t timer/event counter 50 operation csi10 csi11 note serial interface iic0 operable only when external clock is selected as the serial clock multiplier/divider note2 operation stopped power-on-clear function low-voltage detection function external interrupt operable note pd78f0534, 78f0535, 78f0536, 78 f0537, and 78f0537d only. remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f exclks : external subsystem clock f rl : internal low-speed oscillation clock
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 518 cautions 1. to use the peripheral ha rdware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops oscillati ng in the stop mode after the stop mode is released, restart the peripheral hardware. 2. even if ?internal low-speed oscillator can be stopped by software? is selected by the option byte, the internal low-speed osc illation clock continues in the stop mode in the status before the stop mode is set. to stop the internal low- speed oscillator?s oscillation in the stop mode, stop it by software and then execute the stop instruction. 3. to shorten oscillation stabiliz ation time after the stop mode is released when the cpu operates with the high-speed system clock (x1 oscillation) , temporarily switch the cpu clock to the internal high-speed oscillation cl ock before the next execution of the stop instruction. before changing the cpu clock from the internal high-speed oscillation clock to the hi gh-speed system clock (x1 oscillation) after the stop mode is released, check the oscilla tion stabilization time with the oscillation stabilization time counter status register (ostc). 4. if the stop instruction is executed with amph set to 1 when the intern al high-speed oscillation clock or external main system clock is used as the cpu cl ock, the internal high-speed oscillation clock or external main syst em clock is supplied to the cpu 5 s (min.) after the stop mode has been released. (2) stop mode release figure 21-5. operation timing wh en stop mode is released internal high-speed oscillation clock is selected as cpu clock when stop instruction is executed internal high-speed oscillation clock high-speed system clock (x1 oscillation) high-speed system clock (x1 oscillation) is selected as cpu clock when stop instruction is executed stop mode release stop mode clock switched by software internal high-speed oscillation clock high-speed system clock halt status (oscillation stabilization time set by osts) high-speed system clock wait for oscillation accuracy stabilization automatic selection 5 s (typ.) note note when amph = 1 the stop mode can be released by the following two sources.
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 519 (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledg ment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 21-6. stop mode release by interrupt request generation (1) when high-speed system clock is used as cpu clock operating mode (high-speed system clock) operating mode (high-speed system clock) oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped high-speed system clock (x1 oscillation) status of cpu oscillation stabilization time (set by osts) (2) when internal high-speed osc illation clock is used as cpu clock normal operation (internal high-speed oscillation clock) normal operation (internal high-speed oscillation clock) oscillates stop instruction stop mode standby release signal internal high-speed oscillation clock status of cpu oscillation stopped oscillates wait for oscillation accuracy stabilization remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged.
chapter 21 standby function preliminary user?s manual u17260ej3v1ud 520 (b) release by reset signal generation when the reset signal is generated, stop mode is released, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 21-7. stop mode release by reset (1) when high-speed system clock is used as cpu clock stop instruction reset signal high-speed system clock (x1 oscillation) normal operation (high-speed system clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stabilization time (2 11 /f x to 2 16 /f x ) oscillation stopped starting x1 oscillation is specified by software. oscillation stopped reset processing (20 s (typ.)) (2) when internal high-speed osc illation clock is used as cpu clock stop instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped status of cpu oscillates oscillation stopped wait for oscillation accuracy stabilization reset processing (20 s (typ.)) remark f x : x1 clock oscillation frequency table 21-4. operation in response to interrupt request in stop mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 stop mode held reset ? ? reset processing : don?t care
preliminary user?s manual u17260ej3v1ud 521 chapter 22 reset function the following four operations are av ailable to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences . in both cases, program ex ecution starts at the address at 0000h and 0001h when the reset signal is generated. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status shown in tables 22-1 and 22-2. each pin is high impedance during reset signal generation or during the osci llation stabilization time just after a reset release, except for p130, which is low-level output. when a low level is input to the reset pin, the device is reset. it is released from the reset status when a high level is input to the reset pin and program execution is started with the internal high- speed oscillation clock after reset processing. a reset by the watchdog timer is autom atically released, and program execution starts using the internal high-speed oscillation clock (see figures 22-2 to 22-4 ) after reset processing. reset by poc and lvi circuit power supply detection is automatically released when v dd v poc or v dd v lvi after the reset, and program execution starts using the internal high-speed oscillation clock (see chapter 23 power-on-clear circuit and chapter 24 low-voltage detector ) after reset processing. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, the x1 clo ck, xt1 clock, internal high-speed oscillati on clock, and internal low-speed oscillation clock stop oscillating. external main system clock input and external subsystem clock input become invalid. 3. when the stop mode is released by a reset , the stop mode contents are held during reset input. however, the port pins become high-impedance, except fo r p130, which is set to low- level output.
chapter 22 reset function preliminary user?s manual u17260ej3v1ud 522 figure 22-1. block di agram of reset function lvirf wdtrf reset control flag register (resf) internal bus watchdog timer reset signal reset power-on-clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register
chapter 22 reset function preliminary user?s manual u17260ej3v1ud 523 figure 22-2. timing of reset by reset input delay delay (5 s (typ.)) hi-z normal operation cpu clock reset period (oscillation stop) normal operation (internal high-speed oscillation clock) reset internal reset signal port pin (except p130) port pin (p130) note high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock wait for oscillation accuracy stabilization starting x1 oscillation is specified by software. reset processing (20 s (typ.)) note set p130 to high-level output by software. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. figure 22-3. timing of reset du e to watchdog timer overflow normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal hi-z port pin (except p130) port pin (p130) note high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (20 s (typ.)) wait for oscillation accuracy stabilization note set p130 to high-level output by software. caution a watchdog timer internal reset resets the watchdog timer. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal.
chapter 22 reset function preliminary user?s manual u17260ej3v1ud 524 figure 22-4. timing of reset in stop mode by reset input delay normal operation cpu clock reset period (oscillation stop) reset internal reset signal stop instruction execution stop status (oscillation stop) high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock hi-z port pin (except p130) port pin (p130) note starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (20 s (typ.)) wait for oscillation accuracy stabilization delay (5 s (typ.)) note set p130 to high-level output by software. remarks 1. when reset is effected, p130 outputs a low level. if p 130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. 2. for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 23 power-on-clear circuit and chapter 24 low-voltage detector .
chapter 22 reset function preliminary user?s manual u17260ej3v1ud 525 table 22-1. operation st atuses during reset period item during reset period system clock clock supply to the cpu is stopped. f rh operation stopped f x operation stopped (pin is i/o port mode) main system clock f exclk clock input invalid (pin is i/o port mode) f xt operation stopped (pin is i/o port mode) subsystem clock f exclks clock input invalid (pin is i/o port mode) f rl cpu flash memory ram operation stopped port (latch) 00 16-bit timer/event counter 01 note 50 8-bit timer/event counter 51 h0 8-bit timer h1 watch timer watchdog timer clock output buzzer output a/d converter uart0 uart6 csi10 csi11 note serial interface iic0 multiplier/divider note operation stopped power-on-clear f unction operable low-voltage detection function external interrupt operation stopped note pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only. remark f rh : internal high-speed oscillation clock f x : x1 oscillation clock f exclk : external main system clock f xt : xt1 oscillation clock f exclks : external subsystem clock f rl : internal low-speed oscillation clock
chapter 22 reset function preliminary user?s manual u17260ej3v1ud 526 table 22-2. hardware statuses after reset acknowledgment (1/3) hardware after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p7, p12 to p14) (output latches) 00h port mode registers (pm0 to pm7, pm12, pm14) ffh pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12, pu14) 00h internal expansion ram size switching register (ixs) 0ch note 3 internal memory size switching register (ims) cfh note 3 memory bank select register (bank) 00h clock operation mode select register (oscctl) 00h processor clock control register (pcc) 01h internal oscillation mode register (rcm) 80h main osc control register (moc) 80h main clock mode register (mcm) 00h oscillation stabilization time counter status register (ostc) 00h oscillation stabilization time select register (osts) 05h timer counters 00, 01 (tm00, tm01) 0000h capture/compare registers 000, 010, 001, 011 (cr000, cr010, cr001, cr011) 0000h mode control registers 00, 01 (tmc00, tmc01) 00h prescaler mode registers 00, 01 (prm00, prm01) 00h capture/compare control registers 00, 01 (crc00, crc01) 00h 16-bit timer/event counters 00, 0 note 4 timer output control registers 00, 01 (toc00, toc01) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. the initial values of the internal memory size s witching register (ims) and internal expansion ram size switching register (ixs) after a reset release are c onstant (ims = cfh, ixs = 0ch) in all the 78k0/ke2 products, regardless of the internal memory capacity. therefore, after a reset is released, be sure to set the following values for each product. flash memory version (78k0/ke2) ims ixs pd78f0531 04h pd78f0532 c6h pd78f0533 c8h 0ch pd78f0534 cch 0ah pd78f0535 cfh 08h pd78f0536 cch 04h pd78f0537, 78f0537d cch 00h 4. 16-bit timer/event counter 01 is available only in the pd78f0534, 78f 0535, 78f0536, 78f0537, and 78f0537d.
chapter 22 reset function preliminary user?s manual u17260ej3v1ud 527 table 22-2. hardware statuses after reset acknowledgment (2/3) hardware status after reset acknowledgment note 1 timer counters 50, 51 (tm50, tm51) 00h compare registers 50, 51 (cr50, cr51) 00h timer clock selection regist ers 50, 51 (tcl50, tcl51) 00h 8-bit timer/event counters 50, 51 mode control registers 50, 51 (tmc50, tmc51) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h mode registers (tmhmd0, tmhmd1) 00h 8-bit timers h0, h1 carrier control register 1 (tmcyc1) note 2 00h watch timer operation m ode register (wtm) 00h clock output/buzzer output controller clock output selection register (cks) 00h watchdog timer enable register (wdte) 1ah/9ah note 3 10-bit a/d conversion result register (adcr) 0000h 8-bit a/d conversion result register (adcrh) 00h mode register (adm) 00h analog input channel specification register (ads) 00h a/d converter a/d port configuration register (adpc) 00h receive buffer register 0 (rxb0) ffh transmit shift register 0 (txs0) ffh asynchronous serial interface oper ation mode register 0 (asim0) 01h asynchronous serial interface reception error status register 0 (asis0) 00h serial interface uart0 baud rate generator control register 0 (brgc0) 1fh receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface oper ation mode register 6 (asim6) 01h asynchronous serial interface reception error status register 6 (asis6) 00h asynchronous serial interface transmis sion status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh asynchronous serial interface control register 6 (asicl6) 16h serial interface uart6 input switch control register (isc) 00h transmit buffer registers 10, 11 (sotb10, sotb11) 00h serial i/o shift registers 10, 11 (sio10, sio11) 00h serial operation mode registers 10, 11 (csim10, csim11) 00h serial interfaces csi10, csi1 note 4 serial clock selection register s 10, 11 (csic10, csic11) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. 8-bit timer h1 only. 3. the reset value of wdte is dete rmined by the option byte setting. 4. serial interface csi11 is available only in the pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d.
chapter 22 reset function preliminary user?s manual u17260ej3v1ud 528 table 22-2. hardware statuses after reset acknowledgment (3/3) hardware status after reset acknowledgment note 1 shift register 0 (iic0) 00h control register 0 (iicc0) 00h slave address register 0 (sva0) 00h clock selection register 0 (iiccl0) 00h function expansion register 0 (iicx0) 00h status register 0 (iics0) 00h serial interface iic0 flag register 0 (iicf0) 00h remainder data register 0 (sdr0) 0000h multiplication/division data regi ster a0 (mda0h, mda0l) 0000h multiplication/division data register b0 (mdb0) 0000h multiplier/divider note 2 multiplier/divider control register 0 (dmuc0) 00h key interrupt key return mode register (krm) 00h reset function reset control flag register (resf) 00h note 3 low-voltage detection register (lvim) 00h note 3 low-voltage detector low-voltage detection level selection register (lvis) 00h note 3 request flag registers 0l, 0h, 1l, 1h (if0l, if0h, if1l, if1h) 00h mask flag registers 0l, 0h, 1l, 1h (mk0l, mk0h, mk1l, mk1h) ffh priority specification fl ag registers 0l, 0h, 1l, 1h (pr0l, pr0h, pr1l, pr1h) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. multiplier/divider is available only in the pd78f0534, 78f0535, 78f0536 , 78f0537, and 78f0537d. 3. these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by lvi wdtrf bit set (1) held resf lvirf bit cleared (0) cleared (0) held set (1) lvim lvis cleared (00h) cleared (00h) cleared (00h) held
chapter 22 reset function preliminary user?s manual u17260ej3v1ud 529 22.1 register for confirming reset source many internal reset generation sources exist in the 78k0/ ke2. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset by power-on-clear (poc) circuit, and reading resf set resf to 00h. figure 22-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 0 lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 22-3. table 22-3. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by lvi wdtrf set (1) held lvirf cleared (0) cleared (0) held set (1)
preliminary user?s manual u17260ej3v1ud 530 chapter 23 power-on-clear circuit 23.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. in the 1.59 v poc mode (option byte: pocmode = 0), the reset signal is released when the supply voltage (v dd ) exceeds 1.59 v 0.15 v. in the 2.7 v/1.59 v poc m ode (option byte: pocmode = 1), the re set signal is released when the supply voltage (v dd ) exceeds 2.7 v 0.2 v. ? compares supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v), generates internal reset signal when v dd < v poc , and releases reset when v dd v poc . caution if an internal reset signal is generated in the poc circuit, th e reset control flag register (resf) is cleared to 00h. remark this product incorporates multiple hardware functi ons that generate an internal reset signal. a flag that indicates the reset source is located in the reset control flag register (resf) for when an internal reset signal is generated by the watchdog timer (w dt) or low-voltage-detector (lvi). resf is not cleared to 00h and the flag is set to 1 when an in ternal reset signal is generated by wdt or lvi. for details of resf, see chapter 22 reset function .
chapter 23 power-on-clear circuit preliminary user?s manual u17260ej3v1ud 531 23.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 23-1. figure 23-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 23.3 operation of power-on-clear circuit (1) in 1.59 v poc mode (option byte: pocmode = 0) ? an internal reset signal is generated on power application. when the supply voltage (v dd ) exceeds the detection voltage (v poc = 1.59 v 0.15 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v poc . (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) ? an internal reset signal is generated on power application. when the supply voltage (v dd ) exceeds the detection voltage (v ddpoc = 2.7 v 0.2 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v poc . the timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown below.
chapter 23 power-on-clear circuit preliminary user?s manual u17260ej3v1ud 532 figure 23-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. v poc = 1.59 v (typ.) v lvi operation stops wait for voltage stabilization (3.24 ms (typ.)) normal operation (internal high-speed oscillation clock) note 3 operation stops reset period (oscillation stop) reset period (oscillation stop) wait for oscillation accuracy stabilization normal operation (internal high-speed oscillation clock) note 3 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 wait for voltage stabilization (3.24 ms (typ.)) normal operation (internal high-speed oscillation clock ) note 3 0.5 v/ms (max.) note 2 wait for oscillation accuracy stabilization set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt wait for oscillation accuracy stabilization internal reset signal reset processing (20 s (typ.)) reset processing (20 s (typ.)) reset processing (20 s (typ.)) notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, us e the reset function of the low-vo ltage detector, or input the low level to the reset pin. 2. if the voltage rises to 1.8 v at a rate slower t han 0.5 v/ms (max.) on power application, input a low level to the reset pin after power application and be fore the voltage reaches 1.8 v, or set the 2.7 v/1.59 v poc mode by using an option byte (pocmode = 1). 3. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer function for confirmation of the lapse of the stabilization time. caution set the low-voltage detector by software after the reset status is released (see chapter 24 low-voltage detector). remark v lvi : lvi detection voltage v poc : poc detection voltage
chapter 23 power-on-clear circuit preliminary user?s manual u17260ej3v1ud 533 figure 23-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. internal reset signal 2.7 v (typ.) v poc = 1.59 v (typ.) v lvi operation stops normal operation (internal high-speed oscillation clock) note 2 normal operation (internal high-speed oscillation clock) note 2 operation stops reset period (oscillation stop) reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 2 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 wait for oscillation accuracy stabilization wait for oscillation accuracy stabilization wait for oscillation accuracy stabilization reset processing (20 s (typ.)) reset processing (20 s (typ.)) reset processing (20 s (typ.)) set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, us e the reset function of the low-vo ltage detector, or input the low level to the reset pin. 2. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer function for confirmation of the lapse of the stabilization time. caution set the low-voltage detector by software after the reset status is released (see chapter 24 low-voltage detector). remark v lvi : lvi detection voltage v poc : poc detection voltage
chapter 23 power-on-clear circuit preliminary user?s manual u17260ej3v1ud 534 23.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. after releasing the reset signal, wait for the supply vo ltage fluctuation period of each system by means of a software counter that uses a time r, and then initialize the ports. figure 23-3. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or le ss in vicinity of poc detection voltage ; check the reset source note 2 initialize the port. note 1 reset initialization processing <1> 50 ms has passed? (tmifh1 = 1?) initialization processing <2> setting 8-bit timer h1 (to measure 50 ms) ; setting of division ratio of system clock, such as setting of timer or a/d converter yes no power-on-clear clearing wdt ;f prs = internal high-speed oscillation clock (8.4 mhz (max.)) (default) source: f prs (8.4 mhz (max.))/2 12 , where comparison value = 102: ? 50 ms timer starts (tmhe1 = 1). notes 1. if reset is generated again during this period, initialization processing <2> is not started. 2. a flowchart is shown on the next page.
chapter 23 power-on-clear circuit preliminary user?s manual u17260ej3v1ud 535 figure 23-3. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdtrf of resf register = 1? lvirf of resf register = 1? yes
preliminary user?s manual u17260ej3v1ud 536 chapter 24 low-voltage detector 24.1 functions of low-voltage detector the low-voltage detector (lvi ) has the following functions. ? compares supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal interrupt signal or internal reset signal when v dd < v lvi . detection levels (16 levels) of s upply voltage can be changed by software. ? compares a voltage input from an external input pin (exlvi) with the detection voltage (v exlvi = 1.21 v (typ.)), and generates an internal interrupt signal or internal reset signal when exlvi < v exlvi . ? the supply voltage (v dd ) or voltage input from an external input pin (exlvi) can be selected by software. ? interrupt or reset function can be selected by software. ? operable in stop mode. when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag regi ster (resf) is set to 1 if reset occurs. for details of resf, see chapter 22 reset function . 24.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 24-1. figure 24-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + reference voltage source v dd internal bus n-ch low-voltage detection level selection register (lvis) low-voltage detection register (lvim) lvis2 lvis3 lvif intlvi internal reset signal 4 lvisel exlvi/p120/ intp0 lvimd v dd low-voltage detection level selector selector selector
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 537 24.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level selection register (lvis) ? port mode register 12 (pm12)
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 538 (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets lvim to 00h. figure 24-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd <2> lvisel 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: ffbeh after reset: 00h r/w note 1 lvion notes 2, 3 enables low-voltage detection operation 0 disables operation 1 enables operation lvisel note 2 voltage detection selection 0 detects level of supply voltage (v dd ) 1 detects level of input voltage from external input pin (exlvi) lvimd note 2 low-voltage detection operation mode selection 0 ? lvisel = 0: generates interrupt signal when supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: generates interrupt signal when input voltage from external input pin (exlvi) < detection voltage (v exlvi ) 1 ? lvisel = 0: generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: generates internal reset signal when input voltage from external input pin (exlvi) < detection voltage (v exlvi ) lvif note 4 low-voltage detection flag 0 ? lvisel = 0: supply voltage (v dd ) detection voltage (v lvi ), or when operation is disabled ? lvisel = 1: input voltage from external input pin (exlvi) detection voltage (v exlvi ), or when operation is disabled 1 ? lvisel = 0: supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: input voltage from external input pin (exlvi) < detection voltage (v exlvi ) notes 1. bit 0 is read-only. 2. lvion, lvimd, and lvisel are cleared to 0 in the case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. 3. when lvion is set to 1, operation of the com parator in the lvi circuit is started. use software to wait for an operation stabilization time (10 s (max.)) when lvion is set to 1 until the voltage is confirmed at lvif. 4. the value of lvif is output as the interru pt request signal intlvi when lvion = 1 and lvimd = 0. cautions 1. to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 2. input voltage from external input pin (exlvi) must be exlvi < v dd .
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 539 (2) low-voltage detection level selection register (lvis) this register selects the low-voltage detection level. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation input sets lvis to 00h. figure 24-3. format of low-voltage dete ction level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 lvis3 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h r/w lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.24 v 0.1 v) 0 0 0 1 v lvi1 (4.09 v 0.1 v) 0 0 1 0 v lvi2 (3.93 v 0.1 v) 0 0 1 1 v lvi3 (3.78 v 0.1 v) 0 1 0 0 v lvi4 (3.62 v 0.1 v) 0 1 0 1 v lvi5 (3.47 v 0.1 v) 0 1 1 0 v lvi6 (3.32 v 0.1 v) 0 1 1 1 v lvi7 (3.16 v 0.1 v) 1 0 0 0 v lvi8 (3.01 v 0.1 v) 1 0 0 1 v lvi9 (2.85 v 0.1 v) 1 0 1 0 v lvi10 (2.70 v 0.1 v) 1 0 1 1 v lvi11 (2.55 v 0.1 v) 1 1 0 0 v lvi12 (2.39 v 0.1 v) 1 1 0 1 v lvi13 (2.24 v 0.1 v) 1 1 1 0 v lvi14 (2.08 v 0.1 v) 1 1 1 1 v lvi15 (1.93 v 0.1 v) cautions 1. be sure to clear bits 4 to 7 to 0. 2. do not change the value of lvis during lvi operation. 3. when an input voltage from the externa l input pin (exlvi) is detected, the detection voltage (v exlvi = 1.21 v (typ.)) is fixed. therefor e, setting of lvis is not necessary.
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 540 (3) port mode register 12 (pm12) when using the p120/exlvi/intp0 pin for external low-volt age detection potential input, set pm120 to 1. at this time, the output latch of p120 may be 0 or 1. pm12 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm12 to ffh. figure 24-4. format of port mode register 12 (pm12) 0 pm120 1 pm121 2 pm122 3 pm123 4 pm124 5 1 6 1 7 1 symbol pm12 address: ff2ch after reset: ffh r/w pm12n p12n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) 24.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. (1) used as reset ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)), generates an internal reset signal when exlvi < v exlvi , and releases internal reset when exlvi v exlvi . (2) used as interrupt ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an interrupt signal (intlvi) when v dd < v lvi . ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)), and generates an interrupt signal (intlvi) when exlvi < v exlvi . remark lvisel: bit 2 of low-voltage detection register (lvim)
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 541 24.4.1 when used as reset (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection r egister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time (10 s (max.)). <6> wait until it is checked that (supply voltage (v dd ) detection voltage (v lvi )) by bit 0 (lvif) of lvim. <7> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi )). figure 24-5 shows the timing of the internal reset signal generated by the low-volt age detector. the numbers in this timing chart correspond to <1> to <7> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <4>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0.
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 542 figure 24-5. timing of low-voltage dete ctor internal reset signal generation (detects level of supply voltage (v dd )) (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) supply voltage (v dd ) <3> <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <4> <7> clear clear clear <5> wait time lvion flag (set by software) lvimd flag (set by software) h note 1 l lvisel flag (set by software) <6> <2> v lvi v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 22 reset function . remark <1> to <7> in figure 24-5 above correspond to <1> to <7> in the description of ?when starting operation? in 24.4.1 (1) when detecting level of supply voltage (v dd ) .
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 543 figure 24-5. timing of low-voltage dete ctor internal reset signal generation (detects level of supply voltage (v dd )) (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) supply voltage (v dd ) v lvi <3> <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <4> <7> clear clear clear <5> wait time lvion flag (set by software) lvimd flag (set by software) h note 1 l lvisel flag (set by software) <6> <2> 2.7 v (typ.) v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 22 reset function . remark <1> to <7> in figure 24-5 above correspond to <1> to <7> in the description of ?when starting operation? in 24.4.1 (1) when detecting level of supply voltage (v dd ) .
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 544 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time (10 s (max.) note ). <5> wait until it is checked that (input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))) by bit 0 (lvif) of lvim. <6> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when input voltage from external input pin (exlvi) < detection voltage (v exlvi = 1.21 v (typ.))). figure 24-6 shows the timing of the internal reset signal generated by the low-volt age detector. the numbers in this timing chart correspond to <1> to <6> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. 2. if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an intern al reset signal is not generated. 3. input voltage from external input pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0.
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 545 figure 24-6. timing of low-voltage dete ctor internal reset signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) lvi detection voltage (v exlvi ) <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <3> <6> lvion flag (set by software) lvimd flag (set by software) h note 1 lvisel flag (set by software) <5> <2> not cleared not cleared <4> wait time not cleared not cleared not cleared notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 22 reset function . remark <1> to <6> in figure 24-6 above correspond to <1> to <6> in the description of ? when starting operation? in 24.4.1 (2) when detecting level of input voltage from external input pin (exlvi) .
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 546 24.4.2 when used as interrupt (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection r egister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time (10 s (max.)). <6> confirm that ?supply voltage (v dd ) detection voltage (v lvi )? at bit 0 (lvif) of lvim. <7> clear the interrupt request flag of lvi (lviif) to 0. <8> release the interrupt mask flag of lvi (lvimk). <9> clear bit 1 (lvimd) of lvim to 0 (gener ates interrupt signal when supply voltage (v dd ) < detection voltage (v lvi )) (default value). <10> execute the ei instruction (w hen vector interrupts are used). figure 24-7 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <9> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0.
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 547 figure 24-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) supply voltage (v dd ) time <1> note 1 <8> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <4> <6> <7> cleared by software <5> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <9> v lvi v poc = 1.59 v (typ.) note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). remark <1> to <9> in figure 24-7 above correspond to <1> to <9> in the description of ?when starting operation? in 24.4.2 (1) when detecting level of supply voltage (v dd ) .
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 548 figure 24-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) supply voltage (v dd ) time <1> note 1 <8> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <4> <6> <7> cleared by software <5> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <9> v lvi 2.7 v(typ.) v poc = 1.59 v (typ.) note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). remark <1> to <9> in figure 24-7 above correspond to <1> to <9> in the description of ?when starting operation? in 24.4.2 (1) when detecting level of supply voltage (v dd ) .
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 549 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time (10 s (max.)). <5> confirm that ?input voltage fr om external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)? at bit 0 (lvif) of lvim. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> clear bit 1 (lvimd) of lvim to 0 (gener ates interrupt signal when supply voltage (v dd ) < detection voltage (v lvi )) (default value). <9> execute the ei instruction (w hen vector interrupts are used). figure 24-8 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. caution input voltage from external i nput pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0.
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 550 figure 24-8. timing of low-voltage detector interrupt signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) v exlvi time <1> note 1 <7> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag <3> <5> <6> cleared by software <4> wait time lvion flag (set by software) note 2 note 2 lvisel flag (set by software) <2> lvimd flag (set by software) l <8> note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). remark <1> to <8> in figure 24-8 above correspond to <1> to <8> in the description of ?when starting operation? in 24.4.2 (1) when detecti ng level of supply voltage (v dd ) .
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 551 24.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generated. take (b) of action (2) below. in this system, take the following actions. (1) when used as reset after releasing the reset signal, wait for the supply vo ltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports (see figure 24-9 ). (2) when used as interrupt (a) check that ?supply voltage (v dd ) detection voltage (v lvi )? in the servicing routine of the lvi interrupt by using bit 0 (lvif) of the low-voltag e detection register (lvim). clear bi t 0 (lviif) of interrupt request flag register 0l (if0l) to 0. (b) in a system where the supply voltage fluctuation period is long in the vicinity of t he lvi detection voltage, wait for the supply voltage fluctuation per iod, check that ?supply voltage (v dd ) detection voltage (v lvi )? using the lvif flag, and clear the lviif flag to 0. remark if bit 2 (lvisel) of the low voltage detection regist er (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v note )
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 552 figure 24-9. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check the reset source note initialize the port. ; setting of detection level by lvis the low-voltage detector operates (lvion = 1). reset initialization processing <1> 50 ms has passed? (tmifh1 = 1?) initialization processing <2> setting 8-bit timer h1 (to measure 50 ms) ; setting of division ratio of system clock, such as setting of timer or a/d converter yes no setting lvi clearing wdt detection voltage or higher (lvif = 0?) yes lvif = 0 restarting timer h1 (tmhe1 = 0 tmhe1 = 1) no ; the low-voltage detection flag is cleared. ; the timer counter is cleared and the timer is started. lvi reset ;f prs = internal high-speed oscillation clock (8.4 mhz (max.)) (default) source: f prs (8.4 mhz (max.))/2 12 , where comparison value = 102: ? 50 ms timer starts (tmhe1 = 1). note a flowchart is shown on the next page.
chapter 24 low-voltage detector preliminary user?s manual u17260ej3v1ud 553 figure 24-9. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector yes wdtrf of resf register = 1? lvirf of resf register = 1? no
preliminary user?s manual u17260ej3v1ud 554 chapter 25 option byte 25.1 functions of option bytes the flash memory at 0080h to 0084h of the 78k0/ke2 is an option byte area. when power is turned on or when the device is restarted from the reset status, the device automatically referenc es the option bytes and sets specified functions. when using the product, be sure to set t he following functions by using the option bytes. when the boot swap operation is used du ring self-programming, 0080h to 0084h are switched to 1080h to 1084h. therefore, set values that are the same as thos e of 0080h to 0084h to 1080h to 1084h in advance. (1) 0080h/1080h { internal low-speed oscillator operation ? can be stopped by software ? cannot be stopped { watchdog timer interval time setting { watchdog timer counter operation ? enabled counter operation ? disabled counter operation { watchdog timer window open period setting (2) 0081h/1081h { selecting poc mode ? during 2.7 v/1.59 v poc mode operation (pocmode = 1) the device is in the reset state upon power application and until the supply voltage reaches 2.7 v (typ.). it is released from the reset state when the voltage exceeds 2.7 v (typ.). after that , poc is not detected at 2.7 v but is detect ed at 1.59 v (typ.). if the supply voltage rises to 1.8 v after power applicatio n at a pace slower than 0.5 v/ms (max.), use of the 2.7 v/1.59 v poc mode is recommended. ? during 1.59 v poc mode operation (pocmode = 0) the device is in the reset state upon power application and until the suppl y voltage reaches 1.59 v (typ.). it is released from the reset state when the voltage exceeds 1.59 v (typ.). after that, poc is detected at 1.59 v (typ.), in the same mann er as on power application. (3) 0084h/1084h { on-chip debug operation control ? disabling on-chip debug operation ? enabling on-chip debug operation and erasing data of th e flash memory in case authentication of the on- chip debug security id fails ? enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security id fails cautions 1. be sure to set 00h (disabling on-chip debug operation) to 0084h for products not equipped with the on-chip debug function ( pd78f0531, 78f0532, 78f0 533, 78f0534, 78f0535, 78f0536, and 78f0537). also set 00h to 1084h because 0084h and 1084h are switched at boot swapping. 2. to use the on-chip debug function with a product equipped with the on-chip debug function ( pd78f0537d), set 02h or 03h to 0084h. set a value that is the same as that of 0084h to 1084h because 0084h and 1084h ar e switched at boot swapping. caution be sure to set 00h to 0082h and 0083h (0082h/1082h and 0083h/1083h when the boot swap function is used).
chapter 25 option byte preliminary user?s manual u17260ej3v1ud 555 25.2 format of option byte the format of the option byte is shown below. figure 25-1. format of option byte (1/2) address: 0080h/1080h note 7 6 5 4 3 2 1 0 0 window1 window0 wdton wdcs2 wdcs1 wdcs0 lsrosc window1 window0 watchdog timer window open period 0 0 25% 0 1 50% 1 0 75% 1 1 100% wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped afte r reset), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled wdcs2 wdcs1 wdcs0 watc hdog timer overflow time 0 0 0 2 10 /f rl (3.88 ms) 0 0 1 2 11 /f rl (7.76 ms) 0 1 0 2 12 /f rl (15.52 ms) 0 1 1 2 13 /f rl (31.03 ms) 1 0 0 2 14 /f rl (62.06 ms) 1 0 1 2 15 /f rl (124.12 ms) 1 1 0 2 16 /f rl (248.24 ms) 1 1 1 2 17 /f rl (496.48 ms) lsrosc internal low-speed oscillator operation 0 can be stopped by software (stopped when 1 is written to bit 0 (lsrstop) of rcm register) 1 cannot be stopped (not stopped even if 1 is written to lsrstop bit) note set a value that is the same as that of 0080h to 1080h because 0080h and 1080h are switched during the boot swap operation. cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer does not stop duri ng self-programming of th e flash memory and eeprom emulation. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. 3. if lsrosc = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the halt and stop modes, rega rdless of the setting of bit 0 (lsrstop) of the internal oscillation mode register (rcm). when 8-bit timer h1 operates with the internal low-speed oscillation clo ck, the count clock is supplied to 8-bit timer h1 even in the halt/stop mode. 4. be sure to clear bit 7 to 0. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 264 khz (max.)
chapter 25 option byte preliminary user?s manual u17260ej3v1ud 556 figure 25-1. format of option byte (2/2) address: 0081h/1081h notes 1, 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 pocmode pocmode poc mode selection 0 1.59 v poc mode (default) 1 2.7 v/1.59 v poc mode notes 1. pocmode can only be written by using a dedicat ed flash programmer. it cannot be set during self- programming or boot swap operation during self-programming (at this time, 1.59 v poc mode (default) is set). however, because the value of 1081h is copied to 0081h during the boot swap operation, it is recommended to set a value that is the same as that of 0081h to 1081h w hen the boot swap function is used. 2. to change the setting for the poc mode, set the va lue to 0081h again after batch erasure (chip erasure) of the flash memory. the setting cannot be changed after t he memory of the specified block is erased. caution be sure to clea r bits 7 to 1 to 0. address: 0082h/1082h, 0083h/1083h note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 note be sure to set 00h to 0082h and 0083h, as these addresses are reserved areas. also set 00h to 1082 and 1083h because 0082h and 0083h are switched with 1082h and 1083h when the boot swap operation is used. address: 0084h/1084h notes1, 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ocden1 ocden0 ocden1 ocden0 on-chip debug operation control 0 0 operation disabled 0 1 setting prohibited 1 0 operation enabled. does not erase data of the flash memory in case authentication of the on-chip debug security id fails. 1 1 operation enabled. erases data of the flash memory in case authentication of the on-chip debug security id fails. notes 1. be sure to set 00h (on-chip debug operation di sabled) to 0084h for products not equipped with the on- chip debug function ( pd78f0531, 78f0532, 78f0533, 78f0534, 78f0535, 78f0536, and 78f0537). also set 00h to 1084h because 0084h and 1084h are switched at boot swapping. 2. to use the on-chip debug function with a pr oduct equipped with the on-chip debug function ( pd78f0537d), set 02h or 03h to 0084h. set a val ue that is the same as that of 0084h to 1084h because 0084h and 1084h are switched at boot swapping. remark for the on-chip debug security id, see chapter 27 on-chip debug function ( pd78f0537d only) .
chapter 25 option byte preliminary user?s manual u17260ej3v1ud 557 here is an example of description of t he software for setting the option bytes. opt cseg at 0080h option: db 30h ; enables watchdog timer operation (illegal access detection operation), ; window open period of watchdog timer: 50%, ; overflow time of watchdog timer: 2 10 /f rl , ; internal low-speed oscillator can be stopped by software. db 00h ; 1.59 v poc mode db 00h ; reserved area db 00h ; reserved area db 00h ; on-chip debug operation disabled remark referencing of the option byte is performed during reset processing. for the reset processing timing, see chapter 22 reset function .
preliminary user?s manual u17260ej3v1ud 558 chapter 26 flash memory the 78k0/ke2 incorporates the flash memory to which a program can be written, er ased, and overwritten while mounted on the board. 26.1 internal memory size switching register the internal memory capacity can be selected using t he internal memory size s witching register (ims). ims is set by an 8-bit memory manipulation instruction. reset signal generation sets ims to cfh. caution be sure to set each produc t to the values shown in table 26-1 after a reset release. figure 26-1. format of internal memo ry size switching register (ims) address: fff0h after reset: cfh r/w symbol 7 6 5 4 3 2 1 0 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal hi gh-speed ram capacity selection 0 0 0 768 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 0 1 0 0 16 kb 0 1 1 0 24 kb 1 0 0 0 32 kb 1 1 0 0 48 kb 1 1 1 1 60 kb other than above setting prohibited caution to set the memory size, set im s and then ixs. set the memory si ze so that the internal rom and internal expansion ram areas do not overlap.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 559 table 26-1. internal memory si ze switching register settings flash memory versions (78k0/ke2) ims setting pd78f0531 04h pd78f0532 c6h pd78f0533 c8h pd78f0534 cch pd78f0535 cfh pd78f0536 cch note pd78f0537, 78f0537d cch note note the pd78f0536, pd78f0537, and 78f0537d have internal ro ms of 96 kb and 128 kb, respectively. however, the set values for the ims of these devices is the same as those for the 48 kb product because memory banks are used. for how to set the memory banks, see figure 4-2 format of memory bank select register (bank) .
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 560 26.2 internal expansion ram size switching register the internal expansion ram capacity can be selected using the internal expansion ram size switching register (ixs). ixs is set by an 8-bit memory manipulation instruction. reset signal generation sets ixs to 0ch. caution be sure to set each produc t to the values shown in table 26-2 after a reset release. figure 26-2. format of internal expans ion ram size switching register (ixs) address: fff4h after reset: 0ch r/w symbol 7 6 5 4 3 2 1 0 ixs 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 ixram4 ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 0 1 1 0 0 0 byte 0 1 0 1 0 1024 bytes 0 1 0 0 0 2048 bytes 0 0 1 0 0 4096 bytes 0 0 0 0 0 6144 bytes other than above setting prohibited caution to set memory size, set ims and then ixs. set memory size so that the inte rnal rom area and internal expansion ram area do not overlap. table 26-2. internal expansion ram size switching register settings flash memory versions (78k0/ke2) ixs setting pd78f0531 pd78f0532 pd78f0533 0ch pd78f0534 0ah pd78f0535 08h pd78f0536 04h pd78f0537, 78f0537d 00h
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 561 26.3 writing with flash programmer data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) on-board programming the contents of the flash memory can be rewritten after the 78k0/ke2 has been moun ted on the target system. the connectors that connect the dedicated flash programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedicat ed program adapter (fa seri es) before the 78k0/ke2 is mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. table 26-3. wiring between 78k0/ke 2 and dedicated flash programmer pin configuration of dedicated flas h programmer with csi10 with uart6 signal name i/o pin function pin name pin no. pin name pin no. si/rxd input receive signal so10/p12 44 txd6/p13 43 so/txd output transmit signal si10/rxd0/p11 45 rxd6/p14 42 sck output transfer clock sck10/txd0/p10 46 ? ? clk output clock to 78k0/ke2 ? note 1 ? exclk/x2/p122 note 2 10 /reset output reset signal reset 6 reset 6 flmd0 output mode signal flmd0 9 flmd0 9 v dd 15 v dd 15 ev dd 16 ev dd 16 v dd i/o v dd voltage generation/ power monitoring av ref 47 av ref 47 v ss 13 v ss 13 ev ss 14 ev ss 14 gnd ? ground av ss 48 av ss 48 notes 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart6 is used. when using the clock out of the flash programme r, connect clk and exclk of the programmer.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 562 examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 26-3. example of wiring ad apter for flash memory writing in 3-wire serial i/o (csi10) mode gnd vdd vdd2 writer interface v dd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 si so sck clk /reset flmd0
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 563 figure 26-4. example of wiri ng adapter for flash memory wr iting in uart (uart6) mode gnd vdd vdd2 writer interface gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 si so sck clk /reset flmd0 v dd (2.7 to 5.5 v)
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 564 26.4 programming environment the environment required for writing a program to the fl ash memory of the 78k0/ke2 is illustrated below. figure 26-5. environment for wr iting program to flash memory rs-232c usb 78k0/ke2 flmd0 v dd v ss reset csi10/uart6 host machine dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y yy xxxxx xxxxxx xxxx x x x x y y y y s tat v e a host machine that controls the dedic ated flash programmer is necessary. to interface between the dedicated flash programme r and the 78k0/ke2, csi10 or uart6 is used for manipulation such as writing and erasi ng. to write the flash memory off- board, a dedicated program adapter (fa series) is necessary. 26.5 communication mode communication between the dedicated flash progra mmer and the 78k0/ke2 is established by serial communication via csi10 or uart6 of the 78k0/ke2. (1) csi10 transfer rate: 2.4 khz to 2.5 mhz figure 26-6. communication with de dicated flash programmer (csi10) v dd /ev dd /av ref v ss /ev ss /av ss reset so10 si10 sck10 flmd0 flmd0 v dd gnd /reset si/rxd so/txd sck dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx yyyy statve 78k0/ke2
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 565 (2) uart6 transfer rate: 115200 bps figure 26-7. communication with de dicated flash programmer (uart6) v dd /ev dd /av ref v ss /ev ss /av ss reset txd6 rxd6 v dd gnd /reset si/rxd so/txd exclk clk dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xx xxxx xxxx xxxx yyyy statve flmd0 flmd0 78k0/ke2 if flashpro4 is used as the dedicated flash programme r, flashpro4 generates the following signal for the 78k0/ke2. for details, refer to the flashpro4 manual. table 26-4. pin connection flashpro4 78k0/ke2 connection signal name i/o pin function pin name csi10 uart6 flmd0 output mode signal flmd0 v dd i/o v dd voltage generation/power monitoring v dd , ev dd , av ref gnd ? ground v ss , ev ss , av ss clk output clock output to 78k0/ke2 exclk note 1 { note 2 /reset output reset signal reset si/rxd input receive signal so10/txd6 so/txd output transmit signal si10/rxd6 sck output transfer clock sck10 notes 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart6 is used. when using the clock out of the flash programme r, connect clk and exclk of the programmer. remark : be sure to connect the pin. { : the pin does not have to be connected if the signal is generated on the target board. : the pin does not have to be connected.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 566 26.6 handling of pins on board to write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. first provide a f unction that selects the normal operati on mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize t he state immediately after reset, the pins must be handled as described below. 26.6.1 flmd0 pin in the normal operation mode, 0 v is input to the flmd 0 pin. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. an flmd0 pin connection example is shown below. figure 26-8. flmd0 pin connection example 78k0/ke2 flmd0 dedicated flash programmer connection pin 26.6.2 serial interface pins the pins used by each serial interface are listed below. table 26-5. pins used by each serial interface serial interface pins used csi10 so10, si10, sck10 uart6 txd6, rxd6 to connect the dedicated flash programmer to the pins of a serial interface that is co nnected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 567 (1) signal collision if the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. to avoid this collision, either isolat e the connection with the other device, or make the other device go into an output high-impedance state. figure 26-9. signal collision (i nput pin of serial interface) input pin signal collision dedicated flash programmer connection pin other device output pin in the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. therefore, isolate the signal of the other device. 78k0/ke2 (2) malfunction of other device if the dedicated flash programmer (output or input) is connec ted to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device , causing the device to malfunction. to avoid this malfunction, isolate the connection with the other device. figure 26-10. malfunction of other device pin dedicated flash programmer connection pin other device input pin if the signal output by the 78k0/ke2 in the flash memory programming mode affects the other device, isolate the signal of the other device. pin dedicated flash programmer connection pin other device input pin if the signal output by the dedicated flash programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. 78k0/ke2 78k0/ke2
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 568 26.6.3 reset pin if the reset signal of the dedicated flash programmer is co nnected to the reset pin that is connected to the reset signal generator on the board, signal collision takes place. to prevent this collision, is olate the connection with the reset signal generator. if the reset signal is input from the user system whil e the flash memory programming mode is set, the flash memory will not be correctly programmed. do not input any signal other than the reset signal of the dedicated flash programmer. figure 26-11. signal collision (reset pin) reset dedicated flash programmer connection signal reset signal generator signal collision output pin in the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer. therefore, isolate the signal of the reset signal generator. 78k0/ke2 26.6.4 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately afte r reset. if external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to v dd or v ss via a resistor. 26.6.5 regc pin connect the regc pin to gnd via a capacitor (0.47 f: target) in the same manner as during normal operation. 26.6.6 other signal pins connect x1 and x2 in the same status as in t he normal operation mode when using the on-board clock. to input the operating clock from the programmer, how ever, connect the clock out of the programmer to exclk. cautions 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart6 is used. 26.6.7 power supply to use the supply voltage output of t he flash programmer, connect the v dd pin to v dd of the flash programmer, and the v ss pin to gnd of the flash programmer. however, be sure to connect the v dd and v ss pins to v dd and gnd of the flash programmer to use the power monitor function with the flash programmer. to use the on-board supply voltage, connect in compliance with the normal operation mode. supply the same other power supplies (ev dd , ev ss , av ref , and av ss ) as those in the normal operation mode.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 569 26.7 programming method 26.7.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 26-12. flash memory manipulation procedure start selecting communication mode manipulate flash memory end? yes flmd0 pulse supply no end flash memory programming mode is set 26.7.2 flash memory programming mode to rewrite the contents of the flash memory by using the dedicated fl ash programmer, set the 78k0/ke2 in the flash memory programming mode. to se t the mode, set the flmd0 pin to v dd and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 26-13. flash memory programming mode v dd reset 5.5 v 0 v v dd 0 v flash memory programming mode flmd0 flmd0 pulse v dd 0 v table 26-6. relationship between flmd0 pi n and operation mode after reset release flmd0 operation mode 0 normal operation mode v dd flash memory programming mode
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 570 26.7.3 selecting communication mode in the 78k0/ke2, a communication mode is selected by inpu tting pulses (up to 11 pulses) to the flmd0 pin after the dedicated flash memory programmi ng mode is entered. these flmd0 pu lses are generated by the flash programmer. the following table shows the relationship between the number of pulses and communication modes. table 26-7. communication modes standard setting note 1 communication mode port speed on target frequency multiply rate pins used peripheral clock number of flmd0 pulses f x 0 uart (uart6) uart-ch0 115200 bps note 3 txd6, rxd6 f exclk 3 3-wire serial i/o (csi10) sio-ch0 2.4 khz to 2.5 mhz optional 1 to 20 mhz note 2 1.0 so10, si10, sck10 f rh 8 notes 1. selection items for standard settings on flashpro4. 2. the possible setting range differs depending on the voltage. for details, refer to the chapter of electrical specifications. 3. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. caution when uart6 is select ed, the receive clock is calculated b ased on the reset command sent from the dedicated flash programmer after th e flmd0 pulse has been received. remark f x : x1 clock f exclk : external main system clock f rh : internal high-speed oscillation clock
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 571 26.7.4 communication commands the 78k0/ke2 communicates with the dedi cated flash programmer by using comma nds. the signals sent from the flash programmer to the 78k0/ke2 are called commands, and th e signals sent from the 78k0/ke2 to the dedicated flash programmer are called response. figure 26-14. communication commands command response 78k0/ke2 dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve the flash memory control commands of the 78k0/ke2 are listed in the t able below. all these commands are issued from the programmer and the 78k0/ke2 perform proc essing corresponding to the respective commands. table 26-8. flash memory control commands classification command name function verify batch verify command compares the contents of the entire memory with the input data. erase batch erase command erases t he contents of the entire memory. blank check batch blank check command checks the erasure status of the entire memory. high-speed write command writes data by specifying the write address and number of bytes to be written, and executes a verify check. data write successive write command writes data from the address following that of the high-speed write command executed immediately before, and executes a verify check. status read command obtains the operation status oscillation frequency setting command sets the oscillation frequency erase time setting command sets the erase time for batch erase write time setting command sets the write time for writing data baud rate setting command sets the baud rate when uart is used silicon signature command reads the silicon signature information system setting, control reset command escapes from each status the 78k0/ke2 return a response for the command issued by the dedicated flash programmer. the response names sent from the 78k0/ke2 are listed below. table 26-9. response names response name function ack acknowledges command/data. nak acknowledges illegal command/data.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 572 26.8 security settings the operations shown below can be pe rformed using the security setting command. the security setting is valid when the programming mode is set next. ? disabling batch erase (chip erase) execution of the block erase and batch erase (chip eras e) commands for entire blocks in the flash memory is prohibited by this setting. once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings can no longer be cancelled. caution after the security setting for the batch erase is set, erasure ca nnot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be wr itten, because th e erase command is disabled. ? disabling block erase execution of the block erase command for a specific block in the flash memory is prohibited by this setting. this prohibition setting can be cancelled using the batch erase (chip erase) command. ? disabling write execution of the write and block erase commands for enti re blocks in the flash memory is prohibited by this setting. this prohibition setting can be cancelled using the batch erase (chip erase) command. ? disabling rewriting boot cluster 0 execution of the batch erase (chi p erase) command, block erase command, and write command on boot cluster 0 (0000h to 0fffh) in the flash memo ry is prohibited by this setting. caution if a security setting that rewrites boot cluster 0 has been applied, boot cl uster 0 of that device will not be rewritten. the batch erase (chip erase), block eras e, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. the above security settings are only possible for on-board/off-board programming. each security setting can be used in combination. table 26-10 shows the relationship between the erase a nd write commands when the 78k0/ke2 security function is enabled. table 26-10. relationship between comma nds when security function is enabled command security setting batch erase (chip erase) command block erase command write command disabling batch erase (chip erase) invalid valid note disabling block erase valid disabling write valid disabling rewriting boot cluster 0 invalid invalid invalid note since the erase command is disabled, data different from that which has already been written to the flash memory cannot be written.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 573 table 26-11 shows the relationship between the security setting and the operation in each programming mode. table 26-11. relationship between security se tting and operation in each programming mode on-board/off-board programming self programming programming mode security setting security setting security operation security setting security operation disabling batch erase (chip erase) disabling block erase disabling write disabled invalid note 2 disabling rewriting boot cluster 0 enabled valid note 1 enabled valid notes 1. execution of each command is prohi bited by the security setting. 2. execution of self programming command is possible regardless of the security setting.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 574 26.9 flash memory programming by self-programming the 78k0/ke2 supports a self-programmi ng function that can be used to rewr ite the flash memory via a user program. because this function allows a user application to rewrite the fl ash memory by using the 78k0/ke2 self- programming library, it can be used to upgrade the program in the field. if an interrupt occurs during self-programming, self -programming can be temporarily stopped and interrupt servicing can be executed. to execute interrupt servicing, restore the normal operation mode after self-programming has been stopped, and execute t he ei instruction. after the self-pr ogramming mode is later restored, self- programming can be resumed. remark for details of the self-programming function and the 78k0/ke2 self-programming library, refer to a separate document to be published (document name: 78k0/kx2 applic ation note, release schedule: pending). cautions 1. the self-programmi ng function cannot be used when th e cpu operates with the subsystem clock. 2. input a high level to the fl md0 pin during self-programming. 3. be sure to execute the di instru ction before starting self-programming. the self-programming function checks the interrupt request flags (if0l, if0h, if1l, and if1h). if an interrupt request is gene rated, self-programming is stopped. 4. self-programming is also st opped by an interrupt request that is not masked even in the di status. to prevent this, mask the interrupt by using the interrupt mask flag registers (mk0l, mk0h, mk1l, and mk1h). 5. self-programming is executed with the intern al high-speed oscillati on clock. if the cpu operates with the x1 clock or external main syst em clock, the oscillation stabilization wait time of the internal high-speed oscilla tion clock elapses dur ing self-programming. 6. allocate the entry program for self-progr amming in the common area of 0000h to 7fffh. figure 26-15. operation mode and memory map for se lf-programming ( pd78f0537) memory bank 1 memory bank 4 memory bank 3 memory bank 5 memory bank 2 normal mode flash memory (common area) 0000h 8000h 7fffh ffffh fb00h faffh c000h bfffh f800h f7ffh e000h dfffh ff00h feffh internal high- speed ram internal expansion ram sfr reserved reserved flash memory control firmware rom disable accessing flash memory (memory bank 0) memory bank 1 memory bank 4 memory bank 3 memory bank 5 memory bank 2 self-programming mode flash memory (common area) 0000h 8000h 7fffh ffffh fb00h faffh fa20h fa1fh fa20h fa1fh c000h bfffh f800h f7ffh fa00h f9ffh fa00h f9ffh e000h dfffh ff00h feffh internal high- speed ram internal expansion ram sfr reserved reserved buffer ram buffer ram reserved reserved flash memory control firmware rom disable accessing enable accessing instructions can be fetched from common area and selected memory bank. instructions can be fetched from common area and firmware rom.
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 575 the procedure of self-program ming is illustrated below. figure 26-16. self-programming procedure execute ei instruction secure entry ram area execute di instruction flmd0 pin = high level start self-programming flmd0 pin = low level confirm library return value end of self-programming entry program (user program) library entry program (user program) set parameters to entry ram execute library and access flash memory according to library contents no interrupt request interrupt request interrupt servicing self-programming being suspended
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 576 26.9.1 boot swap function if rewriting the boot area has failed dur ing self-programming due to a power fa ilure or some other cause, the data in the boot area may be lost and the pr ogram may not be restarted by resetting. the boot swap function is used to avoid this problem. before erasing boot cluster 0 note , which is a boot program area, by self-p rogramming, write a new boot program to boot cluster 1 in advance. when the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firm ware of the 78k0/ke2, so that boot cluster 1 is used as a boot area. after that, erase or write the or iginal boot program area, boot cluster 0. as a result, even if a power failure occurs while the bo ot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. if the program has been correctly written to boot cluster 0, restore the original bo ot area by using the set information function of the firmware of the 78k0/ke2. note a boot cluster is a 4 kb area and boot clusters 0 and 1 are swapped by the boot swap function. boot cluster 0 (0000h to 0fffh ): original boot program area boot cluster 1 (1000h to 1fffh): area subject to boot swap function figure 26-17. boot swap function boot program (boot cluster 0) new boot program (boot cluster 1) user program self-programming to boot cluster 1 self-programming to boot cluster 0 execution of boot swap by firmware execution of boot swap by firmware user program boot program (boot cluster 0) user program new boot program (boot cluster 1) new boot program (boot cluster 0) user program new boot program (boot cluster 1) new boot program (boot cluster 0) user program new boot program (boot cluster 1) boot program (boot cluster 0) user program xxxxh xxxxh 2000h 0000h 1000h 2000h 0000h 1000h boot boot boot boot boot
chapter 26 flash memory preliminary user?s manual u17260ej3v1ud 577 figure 26-18. example of executing boot swapping boot cluster 1 booted by boot cluster 0 booted by boot cluster 1 booted by boot cluster 0 block number erasing block 4 boot cluster 0 program program boot program 1000h 0000h 1000h 0000h 0000h 1000h erasing block 5 writing blocks 5 to 7 boot swap boot swap canceled 3 2 1 0 7 6 5 4 boot program boot program boot program program program program program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program program program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program program erasing block 6 erasing block 7 program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program erasing block 0 erasing block 1 erasing block 2 erasing block 3 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 boot program boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program writing blocks 0 to 3 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program
preliminary user?s manual u17260ej3v1ud 578 chapter 27 on-chip debug function ( pd78f0537d only) the pd78f0537d uses the v dd , flmd0, reset, ocd0a/x1 (or ocd1a/ p31), ocd0b/x2 (or ocd1b/p32), and v ss pins to communicate with the host machine via an on-c hip debug emulator (qb-78k0 mini). whether ocd0a/x1 and ocd1a/p31, or ocd0b/x2 and ocd1 b/p32 are used can be selected. caution the pd78f0537d has an on-chip debug function. do not use this product for mass production because its reliability cannot be guaranteed after the on-chip de bug function has been used, given the issue of the number of times the flash memory can be rewritten. nec electronics does not accept complaints c oncerning this product. figure 27-1. connection example of qb-78k0mini and pd78f0537d (when ocd0a/x1 and ocd0b/x2 are used) v dd pd78f0537d p31 flmd0 ocd0a/x1 ocd0b/ x2 target reset reset_in x2 x1 flmd0 reset v dd reset_out gnd qb-78k0mini target connector gnd note note note make pull-down resistor 470 ? or more. cautions 1. input the clock from the ocd0a/x1 pin during on-chip debugging. 2. control the ocd0a/x1 and ocd0b/x2 pins by externally pulling down the ocd1a/p31 pin or by using an external circuit using the p130 pi n (that outputs a low le vel when the device is reset).
chapter 27 on-chip debug function ( pd78f0537d only) preliminary user?s manual u17260ej3v1ud 579 figure 27-2. connection example of qb-78k0mini and pd78f0537d (when ocd1a and ocd1b are used) qb-78k0mini target connector v dd ocd1b/p32 flmd0 ocd1a/p31 x2 target reset reset_in x2 x1 flmd0 reset v dd reset_out gnd x1 gnd note note pd78f0537d note make pull-down resistor 470 ? or more. 27.1 on-chip debug security id the pd78f0537d has an on-chip debug operation cont rol flag in the flash memory at 0084h (see chapter 25 option byte ) and an on-chip debug security id setting area at 0085h to 008eh. when the boot swap function is used, also set a value that is the same as that of 1084h and 1085h to 108eh in advance, because 0084h, 0085h to 008eh and 1084h, and 1085h to 108eh are switched. for details on the on-chip debug security id, refer to the qb-78k0mini user?s manual (u17029e). table 27-1. on-chip debug security id address on-chip debug security id 0085h to 008eh 1085h to 108eh any id code of 10 bytes
preliminary user?s manual u17260ej3v1ud 580 chapter 28 instruction set this chapter lists each instruction set of the 78k0/ke2 in table form. for details of each operation and operation code, refer to the separate document 78k/0 series instructions user?s manual (u12326e) . 28.1 conventions used in operation list 28.1.1 operand identifier s and specification methods operands are written in the ?operand? column of each instruction in ac cordance with the specification method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more methods, select one of them. uppercase letters and the sym bols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate num eric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 28-1. operand identifi ers and specification methods identifier specification method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol note special function register symbol (16-bit manipulatable register even addresses only) note saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even address only) addr16 addr11 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit da ta transfer instructions) 0800h to 0fffh immediate data or labels 0040h to 007fh immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh c annot be accessed with these operands. remark for special function register symbols, see table 3-6 special function register list .
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 581 28.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag ( ): memory contents indicated by addre ss or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 28.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 582 28.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7 sfr byte a, r note 3 1 2 ? a r r, a note 3 1 2 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5 a sfr sfr, a 2 ? 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5 a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl + byte] 2 8 9 a (hl + byte) [hl + byte], a 2 8 9 (hl + byte) a a, [hl + b] 1 6 7 a (hl + b) [hl + b], a 1 6 7 (hl + b) a a, [hl + c] 1 6 7 a (hl + c) mov [hl + c], a 1 6 7 (hl + c) a a, r note 3 1 2 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? (sfr) a, !addr16 3 8 10 a ? (addr16) a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 583 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 ? 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 ? 8 ax sfrp sfrp, ax 2 ? 8 sfrp ax ax, rp note 3 1 4 ? ax rp rp, ax note 3 1 4 ? rp ax ax, !addr16 3 10 12 ax (addr16) movw !addr16, ax 3 10 12 (addr16) ax 16-bit data transfer xchw ax, rp note 3 1 4 ? ax ? rp a, #byte 2 4 ? a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 ? a, cy a + r r, a 2 4 ? r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 a, cy a + (addr16) a, [hl] 1 4 5 a, cy a + (hl) a, [hl + byte] 2 8 9 a, cy a + (hl + byte) a, [hl + b] 2 8 9 a, cy a + (hl + b) add a, [hl + c] 2 8 9 a, cy a + (hl + c) a, #byte 2 4 ? a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 ? a, cy a + r + cy r, a 2 4 ? r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 a, cy a + (addr16) + c a, [hl] 1 4 5 a, cy a + (hl) + cy a, [hl + byte] 2 8 9 a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy a + (hl + b) + cy 8-bit operation addc a, [hl + c] 2 8 9 a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 584 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a, cy a ? byte saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte a, r note 3 2 4 ? a, cy a ? r r, a 2 4 ? r, cy r ? a a, saddr 2 4 5 a, cy a ? (saddr) a, !addr16 3 8 9 a, cy a ? (addr16) a, [hl] 1 4 5 a, cy a ? (hl) a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) a, [hl + b] 2 8 9 a, cy a ? (hl + b) sub a, [hl + c] 2 8 9 a, cy a ? (hl + c) a, #byte 2 4 ? a, cy a ? byte ? cy saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte ? cy a, r note 3 2 4 ? a, cy a ? r ? cy r, a 2 4 ? r, cy r ? a ? cy a, saddr 2 4 5 a, cy a ? (saddr) ? cy a, !addr16 3 8 9 a, cy a ? (addr16) ? cy a, [hl] 1 4 5 a, cy a ? (hl) ? cy a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) ? cy a, [hl + b] 2 8 9 a, cy a ? (hl + b) ? cy subc a, [hl + c] 2 8 9 a, cy a ? (hl + c) ? cy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) 8-bit operation and a, [hl + c] 2 8 9 a a (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 585 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) or a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) xor a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a ? byte saddr, #byte 3 6 8 (saddr) ? byte a, r note 3 2 4 ? a ? r r, a 2 4 ? r ? a a, saddr 2 4 5 a ? (saddr) a, !addr16 3 8 9 a ? (addr16) a, [hl] 1 4 5 a ? (hl) a, [hl + byte] 2 8 9 a ? (hl + byte) a, [hl + b] 2 8 9 a ? (hl + b) 8-bit operation cmp a, [hl + c] 2 8 9 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 586 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ax, cy ax + word subw ax, #word 3 6 ? ax, cy ax ? word 16-bit operation cmpw ax, #word 3 6 ? ax ? word mulu x 2 16 ? ax a x multiply/ divide divuw c 2 25 ? ax (quotient), c (remainder) ax c r 1 2 ? r r + 1 inc saddr 2 4 6 (saddr) (saddr) + 1 r 1 2 ? r r ? 1 dec saddr 2 4 6 (saddr) (saddr) ? 1 incw rp 1 4 ? rp rp + 1 increment/ decrement decw rp 1 4 ? rp rp ? 1 ror a, 1 1 2 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 time rol a, 1 1 2 ? (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 time rolc a, 1 1 2 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 a 3 ? 0 (hl) 3 ? 0 , (hl) 7 ? 4 a 3 ? 0 , (hl) 3 ? 0 (hl) 7 ? 4 rotate rol4 [hl] 2 10 12 a 3 ? 0 (hl) 7 ? 4 , (hl) 3 ? 0 a 3 ? 0 , (hl) 7 ? 4 (hl) 3 ? 0 adjba 2 4 ? decimal adjust accumulator after addition bcd adjustment adjbs 2 4 ? decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 ? 7 cy sfr.bit cy, a.bit 2 4 ? cy a.bit cy, psw.bit 3 ? 7 cy psw.bit cy, [hl].bit 2 6 7 cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 ? 8 sfr.bit cy a.bit, cy 2 4 ? a.bit cy psw.bit, cy 3 ? 8 psw.bit cy bit manipulate mov1 [hl].bit, cy 2 6 8 (hl).bit cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 587 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit and1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit or1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw. bit 3 ? 7 cy cy psw.bit xor1 cy, [hl].bit 2 6 7 cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 ? 8 sfr.bit 1 a.bit 2 4 ? a.bit 1 psw.bit 2 ? 6 psw.bit 1 set1 [hl].bit 2 6 8 (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 ? 8 sfr.bit 0 a.bit 2 4 ? a.bit 0 psw.bit 2 ? 6 psw.bit 0 clr1 [hl].bit 2 6 8 (hl).bit 0 set1 cy 1 2 ? cy 1 1 clr1 cy 1 2 ? cy 0 0 bit manipulate not1 cy 1 2 ? cy cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 588 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callf !addr11 2 5 ? (sp ? 1) (pc + 2) h , (sp ? 2) (pc + 2) l , pc 15 ? 11 00001, pc 10 ? 0 addr11, sp sp ? 2 callt [addr5] 1 6 ? (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 brk 1 6 ? (sp ? 1) psw, (sp ? 2) (pc + 1) h , (sp ? 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ? 3, ie 0 ret 1 6 ? pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr call/return retb 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr psw 1 2 ? (sp ? 1) psw, sp sp ? 1 push rp 1 4 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 2 ? psw (sp), sp sp + 1 r r r pop rp 1 4 ? rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 ? 10 sp word sp, ax 2 ? 8 sp ax stack manipulate movw ax, sp 2 ? 8 ax sp !addr16 3 6 ? pc addr16 $addr16 2 6 ? pc pc + 2 + jdisp8 unconditional branch br ax 2 8 ? pch a, pc l x bc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 1 conditional branch bnz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 589 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9 pc pc + 3 + jdisp8 if psw.bit = 1 bt [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if psw. bit = 0 bf [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit btclr [hl].bit, $addr16 3 10 12 pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 ? b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 ? c c ? 1, then pc pc + 2 + jdisp8 if c 0 conditional branch dbnz saddr, $addr16 3 8 10 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 sel rbn 2 4 ? rbs1, 0 n nop 1 2 ? no operation ei 2 ? 6 ie 1 (enable interrupt) di 2 ? 6 ie 0 (disable interrupt) halt 2 6 ? set halt mode cpu control stop 2 6 ? set stop mode notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 590 28.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except ?r = a?
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 591 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1
chapter 28 instruction set preliminary user?s manual u17260ej3v1ud 592 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
preliminary user?s manual u17260ej3v1ud 593 chapter 29 electrical specifications (target) cautions 1. these specifications show target values of (t) (s), and (r ) products, which m ay change after device evaluation. 2. the pd78f0537d has an on-chip debug function . do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, given the i ssue of the number of times the flash memory can be rewritten. nec electronics does not accept complain ts concerning this product. absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd + 0.3 note v supply voltage av ss ? 0.5 to +0.3 v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120 to p124, p140, p141, x1, x2, xt1, xt2, reset ? 0.3 to v dd + 0.3 note v input voltage v i2 p60 to p63 (n-ch open drain) ? 0.3 to +6.5 v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an ani0 to ani7 ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v per pin ? 10 ma p00 to p04, p40 to p43, p120, p130, p140, p141 ? 25 ma output current, high i oh total of all pins ? 80 ma p05, p06, p10 to p17, p30 to p33, p50 to p53, p70 to p77 ? 55 ma note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 594 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin 30 ma p00 to p04, p40 to p43, p120, p130, p140, p141 60 ma output current, low i ol total of all pins 200 ma p05, p06, p10 to p17, p30 to p33, p50 to p53, p60 to p63, p70 to p77 140 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ? 40 to +85 c storage temperature t stg ? 40 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 595 x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 1.0 20.0 2.7 v v dd < 4.0 v 1.0 10.0 ceramic resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 1.0 5.0 mhz 4.0 v v dd 5.5 v 1.0 20.0 2.7 v v dd < 4.0 v 1.0 10.0 crystal resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 1.0 5.0 mhz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring leng th as short as possible. do not cross the wiring wi th the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the o scillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the internal high-speed oscillation cl ock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the osc illation stabilization time of the ostc register and oscillation stabiliz ation time select register (osts) after sufficiently evaluating the oscillation stabilization time wit h the resonator to be used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 596 internal oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 7.6 note 2 8.0 note 2 8.4 note 2 mhz 8 mhz internal oscillator in ternal high-speed oscillation clock frequency (f rh ) note 1 1.8 v v dd < 2.7 v 7.6 note 2 8.0 note 2 10.4 note 2 mhz 2.7 v v dd 5.5 v 216 240 264 khz 240 khz internal oscillator internal low-speed oscillation clock frequency (f rl ) 1.8 v v dd < 2.7 v 120 240 264 khz notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. this is the frequency when rsts (bit 7 of the inter nal oscillation mode register (rcm)) = 1. it is 5.6 mhz (typ.) when rsts = 0. xt1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd xt1 clock oscillation frequency (f xt ) note 32 32.768 35 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 oscillator, wire as follows in the area enclosed by the br oken lines in the above figure to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is designed as a low-amplit ude circuit for reducing power consumption, and is more prone to malfunction due to noise than th e x1 oscillator. partic ular care is therefore required with the wiring method when the xt1 clock is used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 597 dc characteristics (1/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 ma 2.7 v v dd < 4.0 v ? 2.5 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p130, p140, p141 1.8 v v dd < 2.7 v ? 1.0 ma 4.0 v v dd 5.5 v ? 20.0 ma 2.7 v v dd < 4.0 v ? 10.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 note 3 1.8 v v dd < 2.7 v ? 5.0 ma 4.0 v v dd 5.5 v ? 30.0 ma 2.7 v v dd < 4.0 v ? 19.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p53, p70 to p77 note 3 1.8 v v dd < 2.7 v ? 10.0 ma 4.0 v v dd 5.5 v ? 50.0 ma 2.7 v v dd < 4.0 v ? 29.0 ma i oh1 total note 3 of all pins 1.8 v v dd < 2.7 v ? 15.0 ma per pin for p20 to p27 av ref = v dd ? 0.1 ma output current, high note 1 i oh2 per pin for p121 to p124 ? 0.1 ma 4.0 v v dd 5.5 v 8.5 ma 2.7 v v dd < 4.0 v 5.0 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p130, p140, p141 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 15.0 ma 2.7 v v dd < 4.0 v 5.0 ma per pin for p60 to p63 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 20.0 ma 2.7 v v dd < 4.0 v 15.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 note 3 1.8 v v dd < 2.7 v 9.0 ma 4.0 v v dd 5.5 v 45.0 ma 2.7 v v dd < 4.0 v 35.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p53, p60 to p63, p70 to p77 note 3 1.8 v v dd < 2.7 v 20.0 ma 4.0 v v dd 5.5 v 65.0 ma 2.7 v v dd < 4.0 v 50.0 ma i ol1 total of all pins note 3 1.8 v v dd < 2.7 v 29.0 ma per pin for p20 to p27 av ref = v dd 0.4 ma output current, low note 2 i ol2 per pin for p121 to p124 0.4 ma notes 1. value of current at which the device operation is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to gnd. 3. specification under conditions where the duty fact or is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7)/(n 0.01) where the duty factor is 50%, i oh = 20.0 ma total output current of pins = (20.0 0.7)/(50 0.01) = 28.0 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 598 dc characteristics (2/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p02, p12, p13, p15, p40 to p43, p50 to p53, p63, p121 to p124 0.7v dd v dd v v ih2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p60 to p62, p70 to p77, p120, p140, p141, reset 0.8v dd v dd v input voltage, high ( pd78f0534, 78f0535, 78f0536, 78f0537, 78f0537d) v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v v ih1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p63, p121 to p124 0.7v dd v dd v v ih2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p60 to p62, p70 to p77, p120, p140, p141, reset 0.8v dd v dd v input voltage, high ( pd78f0531, 78f0532, 78f0533) v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v v il1 p02, p12, p13, p15, p40 to p43, p50 to p53, p63, p121 to p124 0 0.3v dd v v il2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p60 to p62, p70 to p77, p120, p140, p141, reset 0 0.2v dd v input voltage, low ( pd78f0534, 78f0535, 78f0536, 78f0537, 78f0537d) v il3 p20 to p27 av ref = v dd 0 0.3av ref v v il1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p63, p121 to p124 0 0.3v dd v v il2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p60 to p62, p70 to p77, p120, p140, p141, reset 0 0.2v dd v input voltage, low ( pd78f0531, 78f0532, 78f0533) v il3 p20 to p27 av ref = v dd 0 0.3av ref v 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v 2.7 v v dd < 4.0 v, i oh1 = ? 2.5 ma v dd ? 0.5 v v oh1 p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p130, p140, p141 1.8 v v dd < 2.7 v, i oh1 = ? 1.0 ma v dd ? 0.5 v p20 to p27 av ref = v dd , i oh2 = ? 100 a v dd ? 0.5 v output voltage, high v oh2 p121 to p124 i oh2 = ? 100 a v dd ? 0.5 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 599 dc characteristics (3/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd < 4.0 v, i ol1 = 5.0 ma 0.7 v 1.8 v v dd < 2.7 v, i ol1 = 2.0 ma 0.5 v v ol1 p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p130, p140, p141 1.8 v v dd < 2.7 v, i ol1 = 0.5 ma 0.4 p20 to p27 av ref = v dd , i ol2 = 0.4 ma 0.4 v v ol2 p121 to p124 i ol2 = 0.4 ma 0.4 v 4.0 v v dd 5.5 v, i ol3 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol3 = 5.0 ma 0.4 v 2.7 v v dd < 4.0 v, i ol1 = 3.0 ma 0.4 v output voltage, low v ol3 p60 to p63 1.8 v v dd < 2.7 v, i ol1 = 2.0 ma 0.4 v i lih1 p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p60 to p63, p70 to p77, p120, p130, p140, p141 v i = v dd 1 a i lih2 p20 to p27 v i = av ref = v dd 1 a p121 to 124 v i = v dd i/o port mode 1 a input leakage current, high i lih3 x1, x2, xt1, xt2 v i = v dd osc mode 20 a i lil1 p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p60 to p63, p70 to p77, p120, p130, p140, p141 v i = v ss ? 1 a i lil2 p20 to p27 v i = v ss , av ref = v dd ? 1 a p121 to 124 v i = v ss i/o port mode ? 1 a input leakage current, low i lil3 x1, x2, xt1, xt2 v i = v ss osc mode ? 20 a pull-up resistor r u v i = v dd 10 20 100 k ? v il in normal operation mode 0 0.2v dd v flmd0 supply voltage v ih in self-programming mode 0.8v dd v dd v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 600 dc characteristics (4/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit f xh = 20 mhz note 2 , v dd = 5.0 v 4.7 5.8 ma f xh = 10 mhz notes 2, 3 , v dd = 5.0 v 2.5 3.5 ma f xh = 10 mhz notes 2, 3 , v dd = 3.0 v 2.1 3.1 ma f xh = 5 mhz notes 2, 3 , v dd = 3.0 v 1.5 2.2 ma f xh = 5 mhz notes 2, 3 , v dd = 2.0 v 1.2 1.8 ma f rh = 8 mhz, v dd = 5.0 v 1.9 2.7 ma i dd1 note 1 operating mode f sub = 32.768 khz notes 2, 4 , v dd = 5.0 v 17 30 a f xh = 20 mhz note 2 , v dd = 5.0 v 2.2 2.6 ma f xh = 10 mhz notes 2, 3 , v dd = 5.0 v 1.0 1.2 ma f xh = 5 mhz notes 2, 3 , v dd = 3.0 v 0.55 0.65 ma f rh = 8 mhz, v dd = 5.0 v 0.6 0.65 ma i dd2 note 5 halt mode f sub = 32.768 khz notes 2, 4 , v dd = 5.0 v 3.5 20 a supply current i dd3 note 5 stop mode v dd = 5.0 v 1 20 a a/d converter operating current i adc note 6 during conversion at maximum speed 2.3 v av ref v dd 0.86 1.9 ma watchdog timer operating current i wdt note 7 during 240 khz internal low-speed oscillation clock operation 5 10 a lvi operating current i lvi note 8 9 35 a notes 1. total current flowing into the internal power supply (v dd ), including the peripheral operation current (however, the current flowing into the pull-up resist ors of the port, and a/d converter is not included). 2. square-wave input 3. when amph (bit 0 of clock operation mode select register (oscctl)) = 0. 4. when main system clock is stopped 5. total current flowing into the internal power supply (v dd ), including the peripheral operating current (however, the current flowing into the pull-up resistor of the port, a/d converter, watchdog timer, and lvi circuit is not included) 6. current flowing only to the a/d converter. t he current value of the 78k 0/ke2 is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 7. current flowing only to the watchdog timer. t he current value of the 78k 0/ke2 is the sum of i dd2 or i dd3 and i wdt when the watchdog timer operates in the halt or stop mode. 8. current flowing only to the lvi circuit. the current value of the 78k0/ke2 is the sum of i dd2 or i dd3 and i lvi when the lvi circuit operates in the halt or stop mode. remarks 1. f xh : high-speed system clock frequency (x1 clock oscill ation frequency or exte rnal main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillat ion frequency or external subsystem clock frequency)
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 601 ac characteristics (1) basic operation (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 32 s 2.7 v v dd < 4.0 v 0.2 32 s main system clock (f xp ) operation 1.8 v v dd < 2.7 v 0.4 note 1 32 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation 114 122 125 s 4.0 v v dd 5.5 v 1.0 20.0 mhz 2.7 v v dd < 4.0 v 1.0 10.0 mhz external main system clock frequency f exclk 1.8 v v dd < 2.7 v 1.0 5.0 mhz external main system clock input high-level width, low-level width t exclkh , t exclkl (1/f exclk 1/2) ? 1 ns external subsystem clock frequency f exclks 32 32.768 35 khz external subsystem clock input high-level width, low-level width t exclksh , t exclksl (1/f exclks 1/2) ? 5 ns 4.0 v v dd 5.5 v 2/f sam + 0.1 note 3 s ti000, ti010, ti001 note 2 , ti011 note 2 input high-level width, low-level width t tih0 , t til0 2.7 v v dd < 4.0 v 2/f sam + 0.2 note 3 s 4.0 v v dd 5.5 v 10 mhz 2.7 v v dd < 4.0 v 10 mhz ti50, ti51 input frequency f ti5 1.8 v v dd < 2.7 v 5 mhz 4.0 v v dd 5.5 v 50 ns 2.7 v v dd < 4.0 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 1.8 v v dd < 2.7 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s key interrupt input low-level width t kr 250 ns reset low-level width t rsl 10 s notes 1. 0.38 s when operating with the 8 mhz internal oscillator. 2. pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only. 3. selection of f sam = f prs , f prs /4, f prs /256, or f prs , f prs /16, f prs /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode re gisters 00 and 01 (prm00, prm01). note that when selecting the ti000 or ti001 vali d edge as the count clock, f sam = f prs.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 602 t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 1.8 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range ac timing test points (excluding ex ternal main system clock a nd external subsystem clock) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd external main system clock timing , external subsystem clock timing exclk 0.7v dd (min.) 0.3v dd (max.) 1/f exclk t exclkl t exclkh 1/f exclks t exclksl t exclksh exclks 0.7v dd (min.) 0.3v dd (max.)
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 603 ti timing ti000, ti010, ti001 note , ti011 note t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl note pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only.
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 604 (2) serial interface (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) (a) uart6 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps (b) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps (c) iic0 standard mode high-speed mode parameter symbol min. max. min. max. unit scl0 clock frequency f scl 0 100 0 400 khz setup time of start/restart condition note 1 t su:sta 4.8 ? 0.7 ? s hold time t hd:sta 4.1 ? 0.7 ? (s hold time when scl0 = ?l? tlow 5.0 ? 1.25 ? (s hold time when scl0 = ?h? thigh 5.0 ? 1.25 ? (s data setup time (reception) tsu:dat 0 ? 0 ? (s data hold time (transmission)note 2 thd:dat 0.47 4.0 0.23 1.00 (s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wa it state is inserted in the ack (acknowledge) timing. (d) csi1n (master mode, sck1n... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 100 ns 2.7 v v dd < 4.0 v 200 ns sck1n cycle time t kcy1 1.8 v v dd < 2.7 v 400 ns sck1n high-/low-level width t kh1 , t kl1 t kcy1 /2 ? 10 note 1 ns si1n setup time (to sck1n ) t sik1 30 ns si1n hold time (from sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 50 pf note 2 40 ns notes 1. this value is when high-speed system clock (f xh ) is used. 2. c is the load capacitance of the sck1n and so1n output lines. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 605 (e) csi1n (slave mode, sck1 n... external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (from sck1n ) t ksi2 50 ns delay time from sck1n to so1n output t kso2 c = 50 pf note 120 ns note c is the load capacitance of the so1n output line. remark n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f0 536, 78f0537, 78f0537d
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 606 serial transfer timing iic0: t low t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t hd:sta t hd:dat scl0 sda0 csi1n: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0: pd78f0531, 78f0532, 78f0533 n = 0, 1: pd78f0534, 78f0535, 78f05 36, 78f0537, 78f0537d
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 607 a/d converter characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 2.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 10 bit 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr overall error notes 1, 2 a inl 2.3 v av ref < 2.7 v 1.2 %fsr 4.0 v av ref 5.5 v 6.1 36.7 s 2.7 v av ref < 4.0 v 12.2 36.7 s conversion time t conv 2.3 v av ref < 2.7 v 27 66.6 s 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr zero-scale error notes 1, 2 e zs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr full-scale error notes 1, 2 e fs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb integral non-linearity error note 1 i le 2.3 v av ref < 2.7 v 6.5 lsb 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb differential non-linearity error note 1 d le 2.3 v av ref < 2.7 v 2.0 %fsr analog input voltage v ain av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 1.59 v poc circuit characteristics (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc 1.44 1.59 1.74 v power voltage rise inclination t pth v dd : 0 v change inclination of v poc 0.5 v/ms minimum pulse width t pw 200 s poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pw
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 608 supply voltage rise time (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 1.8 v (v dd (min.)) (v dd : 0 v 1.8 v) t pup1 pocmode (option byte) = 0, when reset input is not used 3.6 ms maximum time to rise to 1.8 v (v dd (min.)) (releasing reset input v dd : 1.8 v) t pup2 pocmode (option byte) = 0, when reset input is used 1.9 ms supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used supply voltage (v dd ) time 1.8 v t pup1 supply voltage (v dd ) time 1.8 v t pup2 v poc reset pin 2.7 v poc circuit characteristics (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage on application of supply voltage v ddpoc pocmode (option bye) = 1 2.50 2.70 2.90 v
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 609 lvi circuit characteristics (t a = ? 40 to +85 c, v poc v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.14 4.24 4.34 v v lvi1 3.99 4.09 4.19 v v lvi2 3.83 3.93 4.03 v v lvi3 3.68 3.78 3.88 v v lvi4 3.52 3.62 3.72 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v v lvi9 2.75 2.85 2.95 v v lvi10 2.60 2.70 2.80 v v lvi11 2.45 2.55 2.65 v v lvi12 2.29 2.39 2.49 v v lvi13 2.14 2.24 2.34 v v lvi14 1.98 2.08 2.18 v supply voltage level v lvi15 1.83 1.93 2.03 v detection voltage external input pin note 1 exlvi exlvi < v dd , 1.8 v v dd 5.5 v 1.21 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the low- voltage detection register (lvim) to 1 to operation stabilization remark v lvi(n ? 1) > v lvin : n = 1 to 15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 610 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the poc detecti on voltage. when the voltage drop s, the data is retained until a poc reset is effected, but data is not re tained when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode
chapter 29 electrical specifications (target) preliminary user?s manual u17260ej3v1ud 611 flash memory programming characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) (1) basic characteristics parameter symbol conditions min. typ. max. unit v dd supply current i dd f xp = 10 mhz (typ.), 20 mhz (max.) 4.5 11.0 ma all block t eraca 20 200 ms erase time note 1 block unit t erasa 20 200 ms write time t wrwa tbd tbd s number of rewrites per chip c erwr retention: 10 years 1 erase + 1 write after erase = 1 rewrite note 2 100 times notes 1. the prewrite time before erasure and the erase verify time (writeback time) are not included. 2. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. remark f xp : main system clock oscillation frequency (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit time from reset to flmd0 count start t rfcf 4.1 17.1 ms count execution time t count 10.8 13.2 ms flmd0 counter high-/low-level width t ch /t cl t c 0.45 s flmd0 counter rise/fall time t r /t f 12.5 s remark these values may change after evaluation. serial write operation reset flmd0 v dd 0 v v dd 0 v t rfcf t cl t f t r t count t ch t c
preliminary user?s manual u17260ej3v1ud 612 chapter 30 package drawings s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gb-50-ueu-1 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 16 32 1 64 17 33 49 48 64-pin plastic lqfp(fine pitch)(10x10)
chapter 30 package drawings preliminary user?s manual u17260ej3v1ud 613 s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.17 + 0.03 ? 0.06 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.80 0.886 0.15 1.60 0.20 p64gc-80-ubs 3 + 5 ? 3 note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 0.37 + 0.08 ? 0.07 b 16 32 64 17 33 49 48 1 64-pin plastic lqfp(14x14)
chapter 30 package drawings preliminary user?s manual u17260ej3v1ud 614 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end l c lp hd he zd ze l1 a1 a2 a d e 16 32 1 64 17 33 49 48 s y e s x b m a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.125 1.125 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gk-65-uet-1 3 + 5 ? 3 0.32 + 0.08 ? 0.07 b 64-pin plastic lqfp(12x12)
chapter 30 package drawings preliminary user?s manual u17260ej3v1ud 615 s y e s x b m hd he zd ze a1 a2 a d e s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.20 max. 0.10 0.05 1.00 0.05 0.25 c e x y zd ze 0.40 0.07 0.08 0.50 0.50 l lp l1 0.50 0.60 0.15 1.00 0.20 p64ga-40-9ev-1 3 + 5 ? 3 note each lead centerline is located within 0.07 mm of its true position at maximum material condition. 0.18 0.05 b 16 32 1 64 17 33 49 48 l c lp l1 a3 detail of lead end 64-pin plastic tqfp(fine pitch)(7x7)
chapter 30 package drawings preliminary user?s manual u17260ej3v1ud 616 item dimensions d e w e a b x y y1 zd ze 5.00 0.10 5.00 0.10 0.05 0.20 0.91 0.07 0.08 0.50 0.24 0.05 (unit:mm) 0.20 0.75 0.75 s y1 s a s detail of c part y s xab m e 60x b b 0.34 0.05 0.55 0.70 0.05 0.55 0.05 0.70 0.05 0.55 0.05 0.75 0.75 0.55 0.55 r0.17 0.05 r0.17 0.05 r0.12 0.05 r0.12 0.05 r0.275 0.05 r0.35 0.05 0.75 0.55 0.05 0.70 0.05 0.55 0.75 0.55 0.05 0.70 0.05 s wb zd ze index mark b c d a s wa d e 3.90 3.90 detail of d part detail of e part e 1 2 hg f e dc ba 3 4 5 6 7 8 (land pad) (aperture of solder resist) p64fc-50-aa1-1 64-pin plastic flga(5x5)
preliminary user?s manual u17260ej3v1ud 617 chapter 31 cautions for wait 31.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflict s with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conflict, therefore, the cpu repeatedly executes processing, until the correct data is passed. as a result, the cpu does not start the next instruction processing but waits. if this happens, the number of execution clocks of an instruction increas es by the number of wait clocks (for the number of wait clocks, see tables 31-1 ). this must be noted when real-time processing is performed.
chapter 31 cautions for wait preliminary user?s manual u17260ej3v1ud 618 31.2 peripheral hardware that generates wait table 31-1 lists the register s that issue a wait request when accessed by the cpu, and the number of cpu wait clocks. table 31-1. registers that generate wait and number of cpu wait clocks peripheral hardware register access number of wait clocks serial interface uart0 asis0 read 1 clock (fixed) serial interface uart6 asis6 read 1 clock (fixed) serial interface iic0 iics0 read 1 clock (fixed) adm write ads write adpc write adcr read 1 to 5 clocks (when f ad = f prs /2 is selected) 1 to 7 clocks (when f ad = f prs /3 is selected) 1 to 9 clocks (when f ad = f prs /4 is selected) 2 to 13 clocks (when f ad = f prs /6 is selected) 2 to 17 clocks (when f ad = f prs /8 is selected) 2 to 25 clocks (when f ad = f prs /12 is selected) a/d converter the above number of clocks is when the same source clock is selected for f cpu and f prs . the number of wait clocks can be calculated by the following expression and under the following conditions. ? number of wait clocks = {(1/f ad ) 2/(1/f cpu )} + 1 * fraction is truncated if the number of wait clocks 0.5 and rounded up if the number of wait clocks > 0.5. f ad : a/d conversion clock frequency (f prs /2 to f prs /12) f cpu : cpu clock frequency f prs : peripheral hardware clock frequency f xp : main system clock frequency ? maximum number of times: maximum speed of cpu (f xp ), lowest speed of a/d conversion clock (f prs /12) ? minimum number of times: minimum speed of cpu (f sub /2), highest speed of a/d conversion clock (f prs /2) caution when the cpu is operating on the subsystem clock and the peri pheral hardware clock is stopped, do not access the registers listed a bove using an access method in whic h a wait request is issued. remark the clock is the cpu clock (f cpu ).
preliminary user?s manual u17260ej3v1ud 619 appendix a development tools the following development t ools are available for the development of systems that employ the 78k0/ke2. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, pr oducts supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98 ? windows nt tm ? windows 2000 ? windows xp
appendix a development tools preliminary user?s manual u17260ej3v1ud 620 figure a-1. development tool configuration (1/2) (1) when using the in-circu it emulator qb-78k0kx2 language processing software ? assembler package ? c compiler package ? device file ? c library source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) in-circuit emulator note 3 emulation probe target system flash programmer flash memory write adapter flash memory ? software package ? project manager software package flash memory write environment control software (windows only) note 2 power supply unit usb interface cable notes 1. the c library source file is not included in the software package. 2. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows. 3. in-circuit emulator qb-78k0kx2 is supplied with integrated debugger id78k0-qb, simple flash memory programmer pg-fpl3, power supply unit, and usb interface cable. any other products are sold separately.
appendix a development tools preliminary user?s manual u17260ej3v1ud 621 figure a-1. development tool configuration (2/2) (2) when using the on-chip debug emulator qb-78k0mini language processing software ? assembler package ? c compiler package ? device file ? c library source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) usb interface cable on-chip debug emulator note 3 connection cable target connector target system flash programmer flash memory write adapter flash memory ? software package ? project manager software package flash memory write environment control software (windows only) note 2 notes 1. the c library source file is not included in the software package. 2. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows. 3. the on-chip debug emulator qb-78k0mini is su pplied with integrated debugger id78k0-qb, usb interface cable, and connection cable. any other products are sold separately.
appendix a development tools preliminary user?s manual u17260ej3v1ud 622 a.1 software package development tools (software) common to the 78k/0 series are combined in this package. sp78k0 78k/0 series software package part number: s sp78k0 remark in the part number differs depending on the host machine and os used. s sp78k0 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combi nation with a device file (df780547) (sold separately). this assembler package is a dos-based app lication. it can also be used in windows, however, by using the project manager (i ncluded in assembler package) on windows. ra78k0 assembler package part number: s ra78k0 this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler should be used in combination with an assembler package and device file (both sold separately). this c compiler package is a dos-based applic ation. it can also be used in windows, however, by using the project manager (i ncluded in assembler package) on windows. cc78k0 c compiler package part number: s cc78k0 this file contains information peculiar to the device. this device file should be used in combinat ion with a tool (ra78k0, cc78k0, sm+ for 78k0/kx2, and id78k0-qb) (all sold separately). the corresponding os and host machine di ffer depending on the tool to be used. df780547 note 1 device file part number: s df780547 this is a source file of the functions that configure the object library included in the c compiler package. this file is required to match the object lib rary included in the c compiler package to the user?s specifications. cc78k0-l note 2 c library source file part number: s cc78k0-l notes 1. the df780547 can be used in common with t he ra78k0, cc78k0, sm+ for 78k0/kx2, and id78k0- qb. 2. the cc78k0-l is not included in the software package (sp78k0).
appendix a development tools preliminary user?s manual u17260ej3v1ud 623 remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 s cc78k0-l host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4) solaris tm (rel. 2.5.1) cd-rom s df780547 host machine os supply medium ab13 windows (japanese version) bb13 pc-9800 series, ibm pc/at compatibles windows (english version) 3.5-inch 2hd fd a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. the project manager is included in the assembler package (ra78k0). it can only be used in windows. a.4 flash memory writing tools flashpro4 (part number: fl-pr4, pg-fp4) flash memory programmer flash memory programmer dedica ted to microcontrollers with on-chip flash memory. flashpro4 (part number: pg-fpl3) simple flash memory programmer simple flash memory programmer dedicated to microcontrollers with on-chip flash memory. fa-64gb-8eu-a fa-64gc-8bs-a fa-78f0537gk-uet-mx fa-78f0537ga-9ev-mx fa-78f0537fc-aa1-mx flash memory writing adapter flash memory writing adapter used connected to the flashpro4. ? fa-64gb-8eu-a: for 64-pin plastic lqfp (gb-ueu type) ? fa-64gc-8bs-a: for 64-pin plastic lqfp (gc-ubs type) ? fa-78f0537gk-uet-mx: for 64-pi n plastic lqfp (gk-uet type) ? fa-78f0537ga-9ev-mx: for 64-pin plastic tqfp (ga-9ev type) ? fa-78f0537fc-aa1-mx: for 64-pin plastic flga (fc-aa1 type) remark fl-pr4, fa-64ga-8eu-a, fa-64gc-8bs-a, fa -78f0537gk-uet-mx, fa-78f0537ga-9ev-mx, and fa-78f0537fc-aa1-mx are products of na ito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd.
appendix a development tools preliminary user?s manual u17260ej3v1ud 624 a.5 debugging tools (hardware) a.5.1 when using in-circu it emulator qb-78k0kx2 qb-78k0kx2 note 1 in-circuit emulator this in-circuit emulator serves to debug har dware and software when developing application systems using the 78k0/kx2. it supports to the integrated debugger (id78k0-qb). this emulator should be used in combination with a power su pply unit and emulation probe, and the usb is used to connect this emulat or to the host machine. qb-144-ca-01 check pin adapter this check pin adapter is used in waveform monitoring using the oscilloscope, etc. qb-80-ep-01t emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-64gb-ea-04t, qb-64gc-ea-03t, qb-64gk-ea-04t, qb-64ga-ea-01t, qb-64fc-ea-01t exchange adapter this exchange adapter is used to perform pin conver sion from the in-circuit emulator to target connector. ? qb-64gb-ea-04t: 64-pin pl astic lqfp (gb-ueu type) ? qb-64gc-ea-03t: 64-pin pl astic lqfp (gc-ubs type) ? qb-64gk-ea-04t: 64-pin pl astic lqfp (gk-uet type) ? qb-64ga-ea-01t: 64-pin pl astic tqfp (ga-9ev type) ? qb-64fc-ea-01t: 64-pin pl astic flga (fc-aa1 type) qb-64gb-ys-01t, qb-64gc-ys-01t, qb-64gk-ys-01t, qb-64ga-ys-01t space adapter this space adapter is used to adjust the height bet ween the target system and in-circuit emulator. ? qb-64gb-ys-01t: 64-pin pl astic lqfp (gb-ueu type) ? qb-64gc-ys-01t: 64-pin pl astic lqfp (gc-ubs type) ? qb-64gk-ys-01t: 64-pin pl astic lqfp (gk-uet type) ? qb-64ga-ys-01t: 64-pin pl astic tqfp (ga-9ev type) qb-64gb-yq-01t, qb-64gc-yq-01t, qb-64gk-yq-01t, qb-64ga-yq-01t yq connector this yq connector is used to connect the target connector and exchange adapter. ? qb-64gb-yq-01t: 64-pin pl astic lqfp (gb-ueu type) ? qb-64gc-yq-01t: 64-pin pl astic lqfp (gc-ubs type) ? qb-64gk-yq-01t: 64-pin pl astic lqfp (gk-uet type) ? qb-64ga-yq-01t: 64-pin pl astic tqfp (ga-9ev type) qb-64gb-hq-01t, qb-64gc-hq-01t, qb-64gk-hq-01t, qb-64ga-hq-01t mount adapter this mount adapter is used to mount the target device with socket. ? qb-64gb-hq-01t: 64-pin pl astic lqfp (gb-ueu type) ? qb-64gc-hq-01t: 64-pin pl astic lqfp (gc-ubs type) ? qb-64gk-hq-01t: 64-pin pl astic lqfp (gk-uet type) ? qb-64ga-hq-01t: 64-pin pl astic tqfp (ga-9ev type) qb-64gb-nq-01t, qb-64gc-nq-01t, qb-64gk-nq-01t, qb-64ga-nq-01t, qb-64fc-nq-01t target connector this target connector is used to mount on the target system. ? qb-64gb-nq-01t: 64-pin pl astic lqfp (gb-ueu type) ? qb-64gc-nq-01t: 64-pin pl astic lqfp (gc-ubs type) ? qb-64gk-nq-01t: 64-pin pl astic lqfp (gk-uet type) ? qb-64ga-nq-01t: 64-pin pl astic tqfp (ga-9ev type) ? qb-64fc-nq-01t: 64-pin plastic lqfp (fc-aa1 type) note the qb-78k0kx2 is supplied with a power supply unit and usb interface cable. as control software, the integrated debugger id78k0-qb and simple flas h memory programmer pg-fpl3 are supplied.
appendix a development tools preliminary user?s manual u17260ej3v1ud 625 remark the packed contents differ depending on the part number, as follows. packed contents part number in-circuit emulator emulation probe exch ange adapter yq connector target connector qb-78k0kx2-zzz none qb-78k0kx2-t64gb qb-64gb-ea-04t qb-64gb-yq-01t qb-64gb-nq-01t qb-78k0kx2-t64gc qb-64gc-ea-03t qb-64gc-yq-01t qb-64gc-nq-01t qb-78k0kx2-t64gk qb-64gk-ea-04t qb-64gk-yq-01t qb-64gk-nq-01t qb-78k0kx2-t64ga qb-64ga-ea-01t qb-64ga-yq-01t qb-64ga-nq-01t qb-78k0kx2-t64fc qb-78k0kx2 qb-80-ep-01t qb-64fc-ea-01t none qb-64fc-nq-01t a.5.2 when using on-chip debug emulator qb-78k0mini qb-78k0mini note on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0/kx2. it suppo rts the integrated debugger (id78k0-qb). this emulator should be used in combination with a con nection cable and a usb interface cable that is used to connect the host machine. target connector specifications 10-pin general-purpose connec tor (2.54 mm pitch) note the qb-78k0mini is supplied with a usb interface ca ble and a connection cable. as control software, the integrated debugger id78k0-qb is supplied. a.6 debugging tools (software) the sm+ for 78k0/kx2 is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm+ for 78k0/kx2 allows the ex ecution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development e fficiency and software quality. the sm+ for 78k0/kx2 should be used in combination with the device file (df780547) (sold separately). sm+ for 78k0/kx2 system simulator part number: sm780547-b this debugger supports the in-circuit emulator s for the 78k/0 series. the id78k0-qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file (sold separately). id78k0-qb integrated debugger part number: s id78k0-qb remark in the part number differs depending on the host machine and os used. s sm780547-b s id78k0-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom
preliminary user?s manual u17260ej3v1ud 626 appendix b notes on target system design this chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the qb-78k0kx2 is used. figure b-1. for 64-pin gb package 15 10.5 13.375 10 15 10.5 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm)
appendix b notes on target system design preliminary user?s manual u17260ej3v1ud 627 figure b-2. for 64-pin gc package 15 11.85 13.375 10 15 11.85 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) figure b-3. for 64-pin gk package 15 10.5 13.375 10 15 10.5 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm)
preliminary user?s manual u17260ej3v1ud 628 appendix c register index c.1 register index (in alphabetical or der with respect to register names) [a] a/d converter mode register (adm) .............................................................................................. ..............................307 a/d port configuratio n register (adpc) ......................................................................................... ..............................313 analog input channel specification re gister (ads) .............................................................................. ........................312 asynchronous serial interface control register 6 (asi cl6) ...................................................................... ....................360 asynchronous serial interface operat ion mode regist er 0 (a sim0) ................................................................ .............330 asynchronous serial interface operat ion mode regist er 6 (a sim6) ................................................................ .............354 asynchronous serial interface recepti on error status regi ster 0 ( asis0) ........................................................ .............332 asynchronous serial interface recepti on error status regi ster 6 ( asis6) ........................................................ .............356 asynchronous serial interface transmi ssion status regi ster 6 ( asif6) ........................................................... .............357 [b] baud rate generator contro l register 0 (brg c0) ................................................................................. ........................333 baud rate generator contro l register 6 (brg c6) ................................................................................. ........................359 [c] capture/compare contro l register 00 (crc0 0).................................................................................... ........................179 capture/compare contro l register 01 (crc0 1).................................................................................... ........................179 clock operation mode select register (oscctl) .................................................................................. ......................137 clock output selectio n register (cks) .......................................................................................... ...............................301 clock selection regi ster 6 (c ksr6)............................................................................................. ................................358 [e] 8-bit a/d conversion resu lt register (adcrh) ................................................................................... ..........................311 8-bit timer compare re gister 50 (cr50) ......................................................................................... ..............................247 8-bit timer compare re gister 51 (cr51) ......................................................................................... ..............................247 8-bit timer coun ter 50 (t m50).................................................................................................. ....................................247 8-bit timer coun ter 51 (t m51).................................................................................................. ....................................247 8-bit timer h carrier cont rol register 1 (tmc yc1).............................................................................. ..........................270 8-bit timer h compare register 00 (cmp00)...................................................................................... ...........................265 8-bit timer h compare register 01 (cmp01)...................................................................................... ...........................265 8-bit timer h compare register 10 (cmp10)...................................................................................... ...........................265 8-bit timer h compare register 11 (cmp11)...................................................................................... ...........................265 8-bit timer h mode re gister 0 (tmhmd0) ......................................................................................... ...........................266 8-bit timer h mode re gister 1 (tmhmd1) ......................................................................................... ...........................266 8-bit timer mode contro l register 50 (tmc 50)................................................................................... ...........................250 8-bit timer mode contro l register 51 (tmc 51)................................................................................... ...........................250 external interrupt falling edg e enable regist er (egn).......................................................................... ........................497 external interrupt rising e dge enable regist er (egp)........................................................................... ........................497 [i] iic clock selection re gister 0 (iiccl0)........................................................................................ .................................421 iic control regist er 0 ( iicc0) ................................................................................................. ......................................412
appendix c register index preliminary user?s manual u17260ej3v1ud 629 iic flag register 0 (iicf0) .................................................................................................... ........................................419 iic function expansion re gister 0 (iicx0) ...................................................................................... ..............................422 iic shift regist er 0 ( iic0).................................................................................................... ..........................................409 iic status regist er 0 ( iics0) .................................................................................................. ......................................417 input switch contro l register (isc) ............................................................................................ ...................................362 internal expansion ram size switching regi ster (ixs)........................................................................... ......................560 internal memory size s witching regist er (ims) .................................................................................. ..........................558 internal oscillation mode register (rcm)....................................................................................... ..............................141 interrupt mask flag re gister 0h (mk0h) ......................................................................................... .............................495 interrupt mask flag re gister 0l (mk0l)......................................................................................... ...............................495 interrupt mask flag re gister 1h (mk1h) ......................................................................................... .............................495 interrupt mask flag re gister 1l (mk1l)......................................................................................... ...............................495 interrupt request flag register 0h (if0h) ...................................................................................... ...............................493 interrupt request flag register 0l (if 0l) ...................................................................................... ................................493 interrupt request flag register 1h (if1h) ...................................................................................... ...............................493 interrupt request flag register 1l (if 1l) ...................................................................................... ................................493 [k] key return mode re gister (krm) ................................................................................................. ................................507 [l] low-voltage detection level selection regi ster (l vis).......................................................................... ........................538 low-voltage detecti on register (lvim) .......................................................................................... ..............................539 [m] main clock mode register (mcm) ................................................................................................. ...............................143 main osc control register (moc) ................................................................................................ ...............................142 memory bank select register (bank)............................................................................................. ...............................90 multiplication/division data r egister a0 (md a0h, md a0l) ........................................................................ ..................479 multiplication/division dat a register b0 (mdb0)................................................................................ ...........................481 multiplier/divider contro l register 0 (dm uc0) .................................................................................. ............................481 [o] oscillation stabilization time c ounter status r egister (ostc) .................................................................. ............144, 509 oscillation stabilization time select regi ster (osts).......................................................................... ..................145, 510 [p] port mode regist er 0 (p m0)..................................................................................................... .................... 125, 18 7, 392 port mode regist er 1 (p m1)................................................................................................. 125, 252, 270, 334, 362, 392 port mode regist er 2 (p m2)..................................................................................................... ............................125, 314 port mode regist er 3 (p m3)..................................................................................................... ............................125, 252 port mode regist er 4 (p m4)..................................................................................................... ....................................125 port mode regist er 5 (p m5)..................................................................................................... ....................................125 port mode regist er 6 (p m6)..................................................................................................... ............................125, 424 port mode regist er 7 (p m7)..................................................................................................... ....................................125 port mode regist er 12 (p m12)................................................................................................... ..........................125, 540 port mode regist er 14 (p m14)................................................................................................... ..........................125, 303 port regist er 0 (p0)........................................................................................................... ...........................................127
appendix c register index preliminary user?s manual u17260ej3v1ud 630 port regist er 1 (p1)........................................................................................................... ...........................................127 port regist er 2 (p2)........................................................................................................... ...........................................127 port regist er 3 (p3)........................................................................................................... ...........................................127 port regist er 4 (p4)........................................................................................................... ...........................................127 port regist er 5 (p5)........................................................................................................... ...........................................127 port regist er 6 (p6)........................................................................................................... ...........................................127 port regist er 7 (p7)........................................................................................................... ...........................................127 port register 12 (p12) ......................................................................................................... .........................................127 port register 13 (p13) ......................................................................................................... .........................................127 port register 14 (p14) ......................................................................................................... .........................................127 prescaler mode regi ster 00 (prm00)............................................................................................. .............................184 prescaler mode regi ster 01 (prm01)............................................................................................. .............................184 priority specification fl ag register 0h (p r0h) ................................................................................. .............................496 priority specification fl ag register 0l (p r0l) ................................................................................. ..............................496 priority specification fl ag register 1h (p r1h) ................................................................................. .............................496 priority specification fl ag register 1l (p r1l) ................................................................................. ..............................496 processor clock cont rol regist er (pcc) ......................................................................................... ..............................139 pull-up resistor opti on register 0 (pu0) ....................................................................................... ................................128 pull-up resistor opti on register 1 (pu1) ....................................................................................... ................................128 pull-up resistor opti on register 3 (pu3) ....................................................................................... ................................128 pull-up resistor opti on register 4 (pu4) ....................................................................................... ................................128 pull-up resistor opti on register 5 (pu5) ....................................................................................... ................................128 pull-up resistor opti on register 6 (pu6) ....................................................................................... ................................128 pull-up resistor opti on register 7 (pu7) ....................................................................................... ................................128 pull-up resistor opti on register 12 (pu 12) ..................................................................................... ..............................128 pull-up resistor opti on register 14 (pu 14) ..................................................................................... ..............................128 [r] receive buffer regi ster 0 (rxb0) ............................................................................................... .................................329 receive buffer regi ster 6 (rxb6) ............................................................................................... .................................353 remainder data regi ster 0 (sdr0)............................................................................................... ...............................479 reset control flag register (resf) ............................................................................................. .................................529 [s] serial clock selection register 10 (csic10) .................................................................................... .............................390 serial clock selection register 11 (csic11) .................................................................................... .............................390 serial i/o shift regi ster 10 (sio10) ........................................................................................... ...................................387 serial i/o shift regi ster 11 (sio11) ........................................................................................... ...................................387 serial operation mode register 10 (csim 10) ..................................................................................... ..........................388 serial operation mode register 11 (csim 11) ..................................................................................... ..........................388 16-bit timer capture/compar e register 000 (c r000) .............................................................................. ......................173 16-bit timer capture/compar e register 001 (c r001) .............................................................................. ......................173 16-bit timer capture/compar e register 010 (c r010) .............................................................................. ......................173 16-bit timer capture/compar e register 011 (c r011) .............................................................................. ......................173 16-bit timer count er 00 (t m00)................................................................................................. ...................................172 16-bit timer count er 01 (t m00)................................................................................................. ...................................172
appendix c register index preliminary user?s manual u17260ej3v1ud 631 16-bit timer mode contro l register 00 (tmc 00) .................................................................................. .........................176 16-bit timer mode contro l register 01 (tmc 01) .................................................................................. .........................176 16-bit timer output cont rol register 00 (t oc00)................................................................................ ...........................181 16-bit timer output cont rol register 01 (t oc01)................................................................................ ...........................181 slave address regi ster 0 (sva0)................................................................................................ .................................409 [t] timer clock selection register 50 (tcl50) ...................................................................................... ............................248 timer clock selection register 51 (tcl51) ...................................................................................... ............................248 10-bit a/d conversion resu lt register (adcr)................................................................................... ...........................310 transmit buffer regi ster 10 (s otb10)........................................................................................... ..............................386 transmit buffer regi ster 11 (s otb11)........................................................................................... ..............................386 transmit buffer regi ster 6 (txb6).............................................................................................. ..................................353 transmit shift regi ster 0 (txs0) ............................................................................................... ...................................329 [w] watch timer operation mode register (wtm) ...................................................................................... ........................289 watchdog timer enable register (wdte) .......................................................................................... ..........................295
appendix c register index preliminary user?s manual u17260ej3v1ud 632 c.2 register index (in alphabetical or der with respect to register symbol) [a] adcr: 10-bit a/d conver sion result regist er.................................................................................... ....................310 adcrh: 8-bit a/d conver sion result register.................................................................................... ......................311 adm: a/d converte r mode re gister............................................................................................... .....................307 adpc: a/d port config uration r egist er .......................................................................................... .......................313 ads: analog input channel specific ation re gister ............................................................................... ..............312 asicl6: asynchronous serial in terface control register 6....................................................................... ...............360 asif6: asynchronous serial interface transmission status register 6 ............................................................ ......357 asim0: asynchronous serial interf ace operation mode register 0................................................................. .......330 asim6: asynchronous serial interf ace operation mode register 6................................................................. .......354 asis0: asynchronous serial interface re ception error stat us regist er 0......................................................... ......332 asis6: asynchronous serial interface re ception error stat us regist er 6......................................................... ......356 [b] bank: memory bank select re gister .............................................................................................. ...................... 90 brgc0: baud rate generato r control r egister 0 .................................................................................. ...................333 brgc6: baud rate generato r control r egister 6 .................................................................................. ...................359 [c] cks: clock output se lection re gister ........................................................................................... .....................301 cksr6: clock select ion register 6 .............................................................................................. ..........................358 cmp00: 8-bit timer h compare regi ster 00 ....................................................................................... .....................265 cmp01: 8-bit timer h compare regi ster 01 ....................................................................................... .....................265 cmp10: 8-bit timer h compare regi ster 10 ....................................................................................... .....................265 cmp11: 8-bit timer h compare regi ster 11 ....................................................................................... .....................265 cr000: 16-bit timer capture/ compare regi ster 000............................................................................... ................173 cr001: 16-bit timer capture/ compare regi ster 000............................................................................... ................173 cr010: 16-bit timer capture/ compare regi ster 010............................................................................... ................173 cr011: 16-bit timer capture/ compare regi ster 011............................................................................... ................173 cr50: 8-bit timer co mpare regi ster 50.......................................................................................... ......................247 cr51: 8-bit timer co mpare regi ster 51.......................................................................................... ......................247 crc00: capture/compare control regi ster 00 ..................................................................................... ..................179 crc01: capture/compare control regi ster 01 ..................................................................................... ..................179 csic10: serial clock se lection regi ster 10 ..................................................................................... ........................390 csic11: serial clock se lection regi ster 11 ..................................................................................... ........................390 csim10: serial operat ion mode regi ster 10...................................................................................... ......................388 csim11: serial operat ion mode regi ster 11...................................................................................... ......................388 [d] dmuc0: multiplier/divider control re gister 0 ................................................................................... ........................481 [e] egn: external interrupt falling edge enabl e regi ster ........................................................................... ..............497 egp: external interrupt rising edge enabl e regi ster ............................................................................ ..............497
appendix c register index preliminary user?s manual u17260ej3v1ud 633 [i] if0h: interrupt reques t flag regi ster 0h....................................................................................... ......................493 if0l: interrupt reques t flag regi ster 0l ....................................................................................... ......................493 if1h: interrupt reques t flag regi ster 1h....................................................................................... ......................493 if1l: interrupt reques t flag regi ster 1l ....................................................................................... ......................493 iic0: iic shift register 0 ..................................................................................................... ...............................409 iicc0: iic contro l register 0 .................................................................................................. ..............................412 iiccl0: iic clock sele ction regi ster 0 ......................................................................................... ..........................421 iicf0: iic flag register 0..................................................................................................... ................................419 iics0: iic status register 0 ................................................................................................... ..............................417 iicx0: iic function ex pansion regi ster 0....................................................................................... ......................422 ims: internal memory si ze switchin g regi ster ................................................................................... ...............558 isc: input switch control r egist er............................................................................................. ........................362 ixs: internal expansion ram size switchin g regi ster ............................................................................ ..........560 [k] krm: key return mode re gister.................................................................................................. .......................507 [l] lvim: low-voltage de tection re gister ........................................................................................... .....................538 lvis: low-voltage detection level selecti on regi ster ........................................................................... ..............539 [m] mcm: main clo ck mode re gister .................................................................................................. ......................143 mda0h: multiplication/div ision data r egister a0 ................................................................................ ....................479 mda0l: multiplication/div ision data r egister a0 ................................................................................ ....................479 mdb0: multiplication/div ision data r egister b0 ................................................................................. ...................480 mk0h: interrupt mask flag regist er 0h .......................................................................................... ......................495 mk0l: interrupt mask flag regist er 0l.......................................................................................... .......................495 mk1h: interrupt mask flag regist er 1h .......................................................................................... ......................495 mk1l: interrupt mask flag regist er 1l.......................................................................................... .......................495 moc: main osc c ontrol r egister ................................................................................................. ......................142 [o] oscctl: clock operation mode select regist er ................................................................................... ...................137 ostc: oscillation stabilization ti me counter stat us regi ster ................................................................... .....144, 509 osts: oscillation stabilizati on time select register ........................................................................... ..........145, 510 [p] p0: port r egister 0............................................................................................................ ..............................127 p1: port r egister 1............................................................................................................ ..............................127 p2: port r egister 2............................................................................................................ ..............................127 p3: port r egister 3............................................................................................................ ..............................127 p4: port r egister 4............................................................................................................ ..............................127 p5: port r egister 5............................................................................................................ ..............................127 p6: port r egister 6............................................................................................................ ..............................127 p7: port r egister 7............................................................................................................ ..............................127 p12: port r egister 12.......................................................................................................... ..............................127
appendix c register index preliminary user?s manual u17260ej3v1ud 634 p13: port r egister 13 .......................................................................................................... ..............................127 p14: port r egister 14 .......................................................................................................... ..............................127 pcc: processor cloc k control register.......................................................................................... .....................139 pm0: port mode register 0 ...................................................................................................... ..........125, 187, 392 pm1: port mode regist er 1 ........................................................................................ 125, 252, 270, 334, 362, 392 pm2: port mode register 2 ...................................................................................................... ..................125, 314 pm3: port mode register 3 ...................................................................................................... ..................125, 252 pm4: port mode register 4 ...................................................................................................... ..........................125 pm5: port mode register 5 ...................................................................................................... ..........................125 pm6: port mode register 6 ...................................................................................................... ..................125, 424 pm7: port mode register 7 ...................................................................................................... ..........................125 pm12: port mode register 12 .................................................................................................... ..................125, 540 pm14: port mode register 14 .................................................................................................... ..................125, 303 pr0h: priority specificat ion flag r egister 0h .................................................................................. .....................496 pr0l: priority specificat ion flag r egister 0l .................................................................................. ......................496 pr1h: priority specificat ion flag r egister 1h .................................................................................. .....................496 pr1l: priority specificat ion flag r egister 1l .................................................................................. ......................496 prm00: prescaler m ode register 00 .............................................................................................. .......................184 prm01: prescaler m ode register 01 .............................................................................................. .......................184 pu0: pull-up resistor option regi ster 0 ........................................................................................ ......................128 pu1: pull-up resistor option regi ster 1 ........................................................................................ ......................128 pu3: pull-up resistor option regi ster 3 ........................................................................................ ......................128 pu4: pull-up resistor option regi ster 4 ........................................................................................ ......................128 pu5: pull-up resistor option regi ster 5 ........................................................................................ ......................128 pu7: pull-up resistor option regi ster 7 ........................................................................................ ......................128 pu12: pull-up resistor option regi ster 12 ...................................................................................... ......................128 pu14: pull-up resistor option regi ster 14 ...................................................................................... ......................128 [r] rcm: internal oscill ation mode register ........................................................................................ .....................141 resf: reset contro l flag re gister.............................................................................................. ..........................529 rxb0: receive buffe r regist er 0 ................................................................................................ .........................329 rxb6: receive buffe r regist er 6 ................................................................................................ .........................353 [s] sdr0: remainder dat a regist er 0 ................................................................................................ .......................479 sio10: serial i/o sh ift register 10 ............................................................................................ ............................387 sio11: serial i/o sh ift register 11 ............................................................................................ ............................387 sotb10: transmit bu ffer regist er 10 ............................................................................................ ..........................386 sotb11: transmit bu ffer regist er 11 ............................................................................................ ..........................386 sva0: slave addre ss regist er 0................................................................................................. .........................409 [t] tcl50: timer clock sele ction regi ster 50 ....................................................................................... ......................248 tcl51: timer clock sele ction regi ster 51 ....................................................................................... ......................248 tm00: 16-bit time r counter 00.................................................................................................. ...........................172 tm01: 16-bit time r counter 01.................................................................................................. ...........................172
appendix c register index preliminary user?s manual u17260ej3v1ud 635 tm50: 8-bit time r counte r 50 ................................................................................................... ...........................247 tm51: 8-bit time r counte r 51 ................................................................................................... ...........................247 tmc00: 16-bit timer mode control regi ster 00................................................................................... ....................176 tmc01: 16-bit timer mode control regi ster 01................................................................................... ....................176 tmc50: 8-bit timer mode control re gister 50.................................................................................... .....................250 tmc51: 8-bit timer mode control re gister 51.................................................................................... .....................250 tmcyc1: 8-bit timer h carri er control r egister 1 ............................................................................... .......................270 tmhmd0: 8-bit timer h mode regi ster 0.......................................................................................... .........................266 tmhmd1: 8-bit timer h mode regi ster 1.......................................................................................... .........................266 toc00: 16-bit timer output control re gister 00................................................................................. .....................181 toc01: 16-bit timer output control re gister 01................................................................................. .....................181 txb6: transmit buffe r register 6 ............................................................................................... .........................353 txs0: transmit shi ft register 0................................................................................................ ...........................329 [w] wdte: watchdog timer enable re gister ........................................................................................... ...................295 wtm: watch timer oper ation mode regist er ....................................................................................... ...............289
preliminary user?s manual u17260ej3v1ud 636 appendix d revision history d.1 major revisions in this edition (1/7) page description chapter 1 outline pp. 17, 18 addition of note on a product with on-chip debug function to and modification of operating ambient temperature in 1.1 features p. 18 addition of special grade produc ts supporting automotive equipment to 1.2 applications p. 19 modification of 1.3 ordering information p. 23, 24 addition of 64-pin plastic tqfp (7 x7), 64-pin plastic flga (5x5), note to and modification of caution 1 in 1.4 pin configuration (top view) pp. 27, 28 modification of the following items on the function list in 1.5 78k0/kx2 series lineup ? supply voltage range of internal low-speed oscillation clock ? detection voltage of poc ? operating ambient temperature p. 29 addition of pin to ?on-chip debug? in 1.6 block diagram pp. 30, 31 modification of the following items in 1.7 outline of functions ? oscillation frequency range of high-speed system clock ? supply voltage range of internal low-speed oscillation clock ? operating ambient temperature ? package p. 31 modification of outline of timer in 1.7 outline of functions chapter 2 pin functions p. 32 modification of table 2-1 pin i/o buffer power supplies pp. 32 to 35 addition of note to 2.1 pin function list p. 41 modification of descriptions in 2.2.12 av ref p. 41 addition of caution to 2.2.15 regc p. 42 modification of descriptions in 2.2.16 v dd and ev dd , and 2.2.17 v ss and ev ss p. 44 modification of recommended connection of unused pins of p121/x1, p122/x2/exclk, p123/xt1, and p124/xt2/exclks in table 2-2 pin i/o circuit types chapter 3 cpu architecture p. 47 addition of caution 2 to 3.1 memory space p. 47 modification of table 3-1 set values of internal memory size switching register (ims) and internal expansion ram size switching register (ixs) pp. 48 to 55 modification of figure 3-1 memory map ( pd78f0531) to figure 3-8 memory map ( pd78f0537d) p. 57 modification of description in (3) option byte area and (5) on-chip debug security id setting area ( pd78f0537d only) in 3.1.1 p. 58 modification of description in 3.1.2 memory bank ( pd78f0536, 78f0537, and 78f0537d only) pp. 65, 66 addition of note to figure 3-14 correspondence between data memory and addressing ( pd78f0536) and figure 3-15 correspondence between data memory and addressing ( pd78f0537, 78f0537d) p. 77 addition to description in 3.3 instruction address addressing p. 78 addition to description in 3.3.2 immediate addressing p. 79 addition to description in 3.3.3 table indirect addressing p. 82 addition to description in 3.4.3 direct addressing p. 83 modification of [description example] in 3.4.4 short direct addressing
appendix d revision history preliminary user?s manual u17260ej3v1ud 637 (2/7) page description p. 85 addition to description in 3.4.6 register indirect addressing p. 86 addition to description in 3.4.7 based addressing p. 87 addition to description in 3.4.8 based indexed addressing chapter 4 memory bank select function ( pd78f0536, 78f0537, and 78f0537d only) p. 89 addition of chapter chapter 5 port functions p. 99 modification of table 5-1 pin i/o buffer power supplies p. 102 addition of caution to 5.2.1 port 0 p. 102 modification of figure 5-2 block diagram of p00 p. 103 modification of figure 5-3 block diagram of p01 p. 104 modification of figure 5-4 block diagram of p02 p. 105 modification of figure 5-5 block diagram of p03, p05 p. 106 modification of figure 5-6 block diagram of p04 p. 107 modification of figure 5-7 block diagram of p06 p. 108 addition of caution to 5.2.2 port 1 p. 113 addition of description to 5.2.3 port 2 and addition of table 5-4 setting functions of p20/ani0 to p27/ani7 pins p. 121 addition of remark to and modification of caution in 5.2.9 port 12 p. 121 modification of figure 5-22 block diagram of p120 p. 122 modification of figure 5-23 block diagram of p121 to p124 p. 123 addition of a figure to remark in 5.2.10 port 13 p. 129 addition of (4) a/d port configuration register (adpc) to 5.3 registers controlling port function pp. 132, 133 addition of remark 2 and notes 1 and 2 to table 5-5 settings of port mode register and output latch when using alternate function (2/2) chapter 6 clock generator p. 134 modification of oscillation frequency range x1 oscillator and external main system clock in 6.1 (1) main system clock p. 135 addition to description in 6.1 (3) internal low-speed oscillation clock p. 136 modification of figure 6-1 block diagram of clock generator p. 139 modification of figure 6-3 format of processor clock control register (pcc) p. 140 addition of 6.3 (3) setting of operation mode for subsystem clock pin p. 145 modification of description in 6.3 (8) oscillation stabilization time select register (osts) p. 146 modification of oscillation frequency range in 6.4.1 x1 oscillator p. 149 modification of description in 6.4.3 when subsystem clock is not used p. 151 addition of figure 6-12 clock generator operation when power supply voltage is turned on (when 1.59 v poc mode is set (option byte: pocmode = 0)) p. 152 addition of figure 6-13 clock generator operation when power supply voltage is turned on (when 2.7 v/1.59 v poc mode is set (option byte: pocmode = 1)) p. 153 modification of 6.6.1 controlling high-speed system clock p. 156 modification of 6.6.2 example of controlling internal high-speed oscillation clock p. 158 modification of 6.6.3 example of controlling subsystem clock p. 160 modification of description in table 6-4 clocks supplied to cpu and peripheral hardware, and register setting
appendix d revision history preliminary user?s manual u17260ej3v1ud 638 (3/7) page description p. 161 addition of remark to figure 6-14 cpu clock status transition diagram (when 1.59 v poc mode is set (option byte: pocmode = 0)) pp. 162 to 165 modification of the following items in table 6-5 cpu clock transition and sfr register setting examples (3) cpu operating with subsystem clock (d) after reset release (a) (4) cpu clock changing from internal high-speed oscillation clock (b) to high-speed system clock (c) (5) cpu clock changing from internal high-speed oscillation clock (b) to subsystem clock (d) (7) cpu clock changing from high-speed system clock (c) to subsystem clock (d) (9) cpu clock changing from subsystem clock (d) to high-speed system clock (c) p. 166 modification of table 6-6 changing cpu clock p. 167 addition of 6.6.8 time required for switchover of cpu clock and main system clock p. 168 addition of 6.6.9 conditions before clock oscillation is stopped p. 169 addition of 6.6.10 peripheral hardware and source clocks chapter 7 16-bit timer/event counters 00 and 01 p. 170 revision of chapter chapter 8 8-bit timer/event counters 50 and 51 p. 247 modification of description in 8.2 (2) 8-bit timer compare register 5n (cr5n) chapter 9 8-bit timers h0 and h1 p. 264 modification of figure 9-2 block diagram of 8-bit timer h1 p. 265 modification of description in (1) 8-bit timer h compare register 0n (cmp0n) and (2) 8-bit time r h compare register 1n (cmp1n) in 9.2 p. 269 modification of figure 9-6 format of 8-bit timer h mode register 1 (tmhmd1) p. 279 modification of figure 9-12 (e) operation by changing cmp1n (cmp1n = 02h 03h, cmp0n = a5h) p. 280 modification of description in 9.4.3 carrier generator operation (8-bit timer h1 only) p. 281 addition of <3> to figure 9-13 transfer timing p. 282 addition of <8> to setting in 9.4.3 pp. 284, 285 modification of (a) operation when cmp01 = n, cmp11 = n and (b) operation when cmp01 = n, cmp11 = m in figure 9-15 p. 286 modification of description in figure 9-15 (c) operation when cmp11 is changed chapter 11 watchdog timer p. 293 modification of description in 11.1 functions of watchdog timer pp. 296, 297 addition to description in and addition of caution 4 to 11.4.1 controlling operation of watchdog timer chapter 12 clock output/buzzer output controller p. 302 addition of note 1 and cautions 1 and 2 to figure 12-2 format of clock output selection register (cks) chapter 13 a/d converter pp. 305, 306 modification of the following items in 13.2 configuration of a/d converter (2) sample & hold circuit (3) series resistor string (5) successive approximation register (sar) (9) av ref pin p. 309 addition to caution 1 in and addition of caution 4 to table 13-2 a/d conversion time selection p. 312 modification of cautions 2 and 3 in figure 13-8 format of analog input channel specification register (ads) p. 313 modification of description in 13.3 (5) a/d port configuration register (adpc) p. 313 modification of cautions 1 and 2 in figure 13-9 format of a/d port configuration register (adpc)
appendix d revision history preliminary user?s manual u17260ej3v1ud 639 (4/7) page description p. 314 modification of table 13-3 setting functions of ani0/p20 to ani7/p27 pins p. 315 modification of 13.4.1 basic operations of a/d converter p. 316 modification of description in figure 13-11 basic operation of a/d converter p. 317 modification of expression in 13.4.2 input voltage and conversion results pp. 318, 319 modification of description in 13.4.3 a/d converter operation mode pp. 322, 323, 325 modification of the description of the following items in 13.6 cautions for a/d converter (1) operating current in stop mode (4) noise countermeasures (6) input impedance of ani0 to ani7 pins (11) internal equivalent circuit chapter 14 serial interface uart0 p. 326 addition of maximum transfer rate and caution 4 to 14.1 (2) asynchronous serial interface (uart) mode p. 329 addition of caution 1 to 14.2 (3) transmit shift register 0 (txs0) p. 331 addition of caution 5 to figure 14-2 format of asynchronous serial interface operation mode register 0 (asim0) p. 332 modification of description in 14.3 (2) asynchronous serial interface reception error status register 0 (asis0) p. 340 modification of caution 1 in figure 14-9 reception completion interrupt request timing p. 343 addition of table 14-4 set value of tps01 and tps00 chapter 15 serial interface uart6 p. 347 addition of maximum transfer rate and cautions 4 and 5 to 15.1 (2) asynchronous serial interface (uart) mode p. 348 modification of figure 15-1 lin transmission operation p. 349 modification of figure 15-2 lin reception operation p. 353 addition of caution 3 to 15.2 (3) transmit buffer register 6 (txb6) p. 355 addition of cautions 4 and 5 to figure 15-5 format of asynchronous serial interface operation mode register 6 (asim6 ) p. 356 modification of description in 15.3 (2) asynchronous serial interface reception error status register 6 (asis6) p. 361 addition of caution 6 to figure 15-10 format of asynchronous serial interface control register 6 (asicl6) p. 362 modification of description in 15.3 (7) input switch control register (isc) p. 373 modification of caution 1 in 15.4.2 (2) (e) normal reception chapter 16 serial interface csi10, csi11 p. 385 modification of figure 16-1 block diagram of serial interface csi10 p. 386 modification of figure 16-2 block diagram of serial interface csi11 p. 386 modification of caution 2 in 16.2 (1) transmit buffer register 1n (sotb1n) p. 387 modification of caution 2 in 16.2 (2) serial i/o shift register 1n (sio1n) p. 388 modification of note 2 in figure 16-3 format of serial operation mode register 10 (csim10) p. 389 modification of note 2 in figure 16-4 format of serial operation mode register 11 (csim11) p. 390 modification of caution 2 in figure 16-5 format of serial clock selection register 10 (csic10) p. 391 modification of caution 2 in figure 16-6 format of serial clock selection register 11 (csic11) p. 393 modification of note 1 of csim10 and csim11 in 16.4.1 (1) register used
appendix d revision history preliminary user?s manual u17260ej3v1ud 640 (5/7) page description pp. 401, 402 addition of (b) type 3: ckp1n = 1, dap1n = 0 and (d) type 4: ckp1n = 1, dap1n = 1 to figure 16-11 output operation of first bit pp. 403, 404 addition of (b) type 3: ckp1n = 1, dap1n = 0 and (d) type 4: ckp1n = 1, dap1n = 1 in figure 16-12 output value of so1n pin (last bit) chapter 17 serial interface iic0 p. 407 modification of figure 17-1 block diagram of serial interface iic0 p. 409 addition of caution 2 to 17.2 (1) iic shift register 0 (iic0) and addition to description in (2) slave address register 0 (sva0) p. 410 addition of 17.2 (13) stop condition generator p. 413 addition of description to iice0 and addition of caution to figure 17-5 format of iic control register 0 (iicc0) (1/4) p. 414 addition of note 2 to figure 17-5 format of iic control register 0 (iicc0) (2/4) p. 415 addition of description to stt0 in figure 17-5 format of iic control register 0 (iicc0) (3/4) p. 420 addition of clearing condition to stcf and iicbsy in figure 17-7 format of iic flag register 0 (iicf0) p. 421 modification of description in 17.3 (4) iic clock selection register 0 (iiccl0) pp. 422, 423 modification of description in 17.3 (6) i 2 c transfer clock setting method p. 423 modification of table 17-2 selection clock setting p. 428 addition of cause that ack is not returned to 17.5.4 acknowledge (ack) p. 432 addition of 17.5.7 canceling wait p. 437 modification of table 17-6 wait periods and figure 17-20 communication reservation timing p. 440 modification of table 17-7 wait periods pp. 440, 441 addition of (4) to (6) to 17.5.15 other cautions pp. 442, 443 modification of 17.5.16 (1) master operati on (single-master system) and (2) master operation (multi- master system) pp. 447, 448 modification of figure 17-25 slave operation flowchart (1) and figure 17-26 slave operation flowchart (2) p. 450 addition of note to (a) (i) when wtim0 = 0 to and modification of (ii) when wtim0 = 1 in 17.5.17 (1) master device operation p. 451 addition of notes 1 to 3 to ( b) (i) when wtim0 = 0 in 17.5.17 (1) master device operation p. 452 addition of note to (c) (i) when wtim0 = 0 in 17.5.17 (1) master device operation pp. 456, 460, 466, 469 modification of the value of the fo llowing items of iics0 register in 17.5.17 (2) (d) (i) when wtim0 = 0 (after restart, does not match with address (= not extension code)) (2) (d) (ii) when wtim0 = 1 (after restart, do es not match with address (= not extension code)) (3) (d) (i) when wtim0 = 0 (after restart, does not match with address (= not extension code)) (3) (d) (ii) when wtim0 = 1 (after restart, do es not match with address (= not extension code)) (6) (d) (ii) extension code (6) (e) when loss occurs due to stop condition during data transfer (6) (h) (ii) when wtim0 = 1 pp. 461, 463 addition of description to 17.5.17 (5) arbitration loss operation (operation as slave after arbitration loss) and (6) operation when arbitration loss occurs (no communication after arbitration loss)
appendix d revision history preliminary user?s manual u17260ej3v1ud 641 (6/7) page description pp. 467 to 469 addition of description when (i) when wtim0 = 0 to the following items in 17.5.17 (6) operation when arbitration loss occurs (no communication after arbitration loss) ( f) when arbitration loss occurs due to low-level da ta when attempting to generate a restart condition (g) when arbitration loss occurs due to a stop co ndition when attempting to generate a restart condition (h) when arbitration loss occurs due to low-level data when attempting to generate a stop condition pp. 471 to 476 modification of figure 17-27 example of master to slave communication (when 9-clock wait is selected for both master and slave) and figure 17-28 example of slave to master communication (when 8-clock wait is selected for mast er, 9-clock wait is selected for slave) chapter 18 multiplier/divider ( pd78f0534, 78f0535, 78f0536, 78f0537, and 78f0537d only) p. 485 modification of figure 18-7. timing chart of division operation (dcba2586h 0018h) chapter 21 standby function p. 508 modification of caution 3 in 21.1.1 standby function p. 510 modification of description in 21.1.2 (2) oscillation stabilization time select register (osts) pp. 512, 513 addition of clock output and buzzer output to items in and addition of note to table 21-1 operating statuses in halt mode p. 515 modification of figure 21-4 halt mode release by reset p. 517 addition of clock output and buzzer output to items in and addition of note to table 21-3 operating statuses in stop mode p. 518 modification of figure 21-5 operation timing when stop mode is released p. 520 modification of figure 21-7 stop mode release by reset chapter 22 reset function p. 523 modification of figure 22-2 timing of reset by reset input p. 523 modification of figure 22-3 timing of reset due to watchdog timer overflow p. 524 modification of figure 22-4 timing of reset in stop mode by reset input p. 525 addition of clock output and buzzer output to items in table 22-1 operation statuses during reset period p. 528 modification of table in note of table 22-2 hardware statuses after reset acknowledgment (3/3) chapter 23 power-on-clear circuit p. 530 addition of description of 2.7 v/1.59 v poc mode to 23.1 functions of power-on-clear circuit p. 531 modification of 23.3 operation of power-on-clear circuit p. 534 modification of figure 23-3 example of software processing after reset release (1/2) chapter 24 low-voltage detector p. 536 modification of figure 24-1 block diagram of low-voltage detector p. 539 modification of figure 24-3 format of low-voltage de tection level selection register (lvis) p. 543 addition of (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) to figure 24-5 timing of low- voltage detector internal reset signal generation (detects level of supply voltage (v dd )) pp. 547, 548 modification of (1) in 1.59 v poc mode (option byte: pocmode = 0) in and addition of (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) to figure 24-7 timing of low-voltage detector interrupt signal generation (detects level of supply voltage (v dd )) p. 550 modification of figure 24-8 timing of low-voltage detector interrupt signal generation (detects level of input voltage from external input pin (exlvi)) p. 552 modification of figure 24-9 example of software processing after reset release (1/2)
appendix d revision history preliminary user?s manual u17260ej3v1ud 642 (7/7) page description chapter 25 option byte p. 554 modification of description in 25.1 functions of option bytes pp. 555, 556 modification of note in and addition of setting of area 0081h/1081h to 0084h/1084h to figure 25-1 format of option byte p. 557 modification of description example of software for setting the option bytes chapter 26 flash memory p. 558 addition of caution to figure 26-1 format of internal memory size switching register (ims) p. 560 addition of caution to figure 26-2 format of internal expansion ram size switching register (ixs) p. 562 modification of value of v dd in figure 26-3 example of wiring adapter for flash memory writing in 3- wire serial i/o (csi10) mode p. 563 modification of value of v dd in figure 26-4 example of wiring adapter for flash memory writing in uart (uart6) mode pp. 564, 565 modification of transfer rate in (1) csi10 and (2) uart6 in 26.5 p. 570 modification of transfer rate in speed column of table 26-7 communication modes p. 572 addition of 26.8 security settings p. 576 modification of 26.9.1 boot swap function p. 577 modification of figure 26-18 boot swap function chapter 27 on-chip debug function ( pd78f0537d only) p. 578 revision of chapter chapter 29 electrical specifications (target) p. 593 revision of chapter chapter 30 package drawings pp. 612 to 616 addition of package drawing chapter 31 cautions for wait p. 618 modification of of a/d converter in table 31-1 registers that generate wait and number of cpu wait clocks appendix a development tools p. 621 addition of (2) when using the on-chip debug emulator qb-78k0mini to figure a-1 development tool configuration p. 625 addition of a.5.2 when using on-chip debug emulator qb-78k0mini appendix b notes on target system design p. 626 addition of chapter appendix d revision history p. 636 addition of chapter
appendix d revision history preliminary user?s manual u17260ej3v1ud 643 d.2 revision history up to previous edition revisions up to the previous edition are shown below. the ?applied to:? column indicates the chapter in each edition to which the revision was applied. (1/2) edition description applied to addition of only pd78f0537d as on-chip debug function model throughout addition of caution 3 to 1.4 pin configuration (top view) chapter 1 outline addition of description of exscl0 to (2) non-port pins in 2.1 pin function list addition of caution to (2) control mode in 2.2.3 p20 to p27 (port 2) addition of description to (c) exscl0 of (2) control mode in 2.2.7 p60 to p63 (port 6) addition of note 2 to table 2-2 pin i/o circuit types chapter 2 pin functions addition of cautions 1 , 2 , and 3 to 3.1.2 bank area ( pd78f0536, 78f0537, and 78f0537d only) deletion of descriptions of the flpmc, pfcmd, and pfs registers chapter 3 cpu architecture addition of remark to 4.2.7 port 6 modification of output latch setting of p60 and p61 in table 4-4 settings of port mode register and output latch when using alternate function chapter 4 port functions addition of cautions 2 and 3 to figure 5-6 format of clock operation mode select register (oscctl) chapter 5 clock generator 6.4.6 one-shot pulse output operation ? modification of caution 1 in (1) one-shot pulse output with software trigger ? modification of caution in (2) one-shot pulse output with external trigger modification of (a) one-shot pulse output by software and (b) one-shot pulse output with external trigger of (5) re-triggering one-shot pulse in 6.5 cautions for 16-bit timer/event counters 00 and 01 chapter 6 16-bit timer/event counters 00 and 01 modification of caution in (6) asynchronous serial interface control register 6 (asicl6) of 14.3 registers controlling serial interface uart6 modification of cautions 1 , 2 , and 4 in figure 14-10 format of asynchronous serial interface control register 6 (asicl6) chapter 14 serial interface uart6 modification of description in (7) port mode register 6 (pm6) of 16.3 registers to control serial interface iic0 addition of ?wrel0 = wtim0 = 1? to ?acke0 = 0? in figure 16-23 master operation flowchart (1) and figure 16-24 master operation flowchart (2) chapter 16 serial interface iic0 modification of 20.2.1 halt mode addition of caution 4 to table 20-3 operating statuses in stop mode chapter 20 standby function addition of note to figure 22-2 timing of internal reset signal generation in power-on-clear circuit chapter 22 power- on-clear circuit change of value of operation stabilization time in chapter 23 low-voltage detector to 10 s (typ.) and addition of note ?this value may change after evaluation.? chapter 23 low- voltage detector modification of transfer rate in 25.6 (2) uart6 modification of transfer rate and deletion of notes 2 in speed column of uart in table 25-7. communication modes 2nd edition modification of description in 25.9 flash memory programming by self-writing chapter 25 flash memory
appendix d revision history preliminary user?s manual u17260ej3v1ud 644 (2/2) edition description applied to total revision of chapter 26 on-chip debug function ( pd78f0537d only) chapter 26 on- chip debug function ( pd78f0537d only) total revision of chapter 28 electrical specifications (target) chapter 28 electrical specifications (target) 2nd edition total revision of appendix a development tools appendix a development tools

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